VHDL Error simulating a Mealy Finite State Machine sequence detector - vhdl

Question

I'm writing code for a Mealy FSM sequence detector with detection of input sequences 01110010 and 00100111. Overlapping is allowed.
I can compile both the code and had set the top level to the testbench but when I simulate I'm not getting any waveform.
This is the circuit code
library ieee;
use ieee.std_logic_1164.ALL;
entity SequenceDetector_8bit is
port( X : in std_logic;
RST: in std_logic;
CLK: in std_logic;
Z : out std_logic);
end SequenceDetector_8bit;
architecture Behavior of SequenceDetector_8bit is
type state is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13);
signal PresentState, NextState : state;
signal Z0: std_logic;
begin
clk_process:process(CLK,RST)
begin
if RST = '1' then
PresentState <= S0;
elsif rising_edge(CLK) then
PresentState <= NextState;
end if;
end process clk_process;
state_process: process(PresentState, X) -- process executed if state variables.
begin
case PresentState is -- check present state,
when S0 => -- when present state is state-S0
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S1; -- and advance to state-S1
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and stay back at state-S0
end if;
when S1 => -- when present state is state-S1
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S2; -- and advance to state-S2
end if;
when S2 => -- when present state is state-S2
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S3 => -- when present state is state-S3
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S4; -- and advance to state-S4
end if;
when S4 => -- when present state is state-S0
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S5; -- and advance to state-S5
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
end if;
when S5 => -- when present state is state-S5
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S6; -- and advance to state-S6
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S2; -- and advance to state-S2
end if;
when S6 => -- when present state is state-S6
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S7; -- and advance to state-S7
end if;
when S7 => -- when present state is state-S7
if (X='0') then -- and when input X = 0,
Z0 <= '1'; -- produce output 1
NextState <= S10; -- and advance to state-S10
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S8 => -- when present state is state-S8
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and stay back at state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 1
NextState <= S9; -- and advance to state-S9
end if;
when S9 => -- when present state is state-S9
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S10; -- and advance to state-S10
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S10 => -- when present state is state-S10
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S11; -- and advance to state-S11
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S12; -- and advance to state-S12
end if;
when S11 => -- when present state is state-S11
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S12; -- and advance to state-S12
end if;
when S12 => -- when present state is state-S12
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S13; -- and advance to state-S13
end if;
when S13 => -- when present state is state-S13
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S1; -- and advance to state-S1
else -- when input X = 1,
Z0 <= '1'; -- produce output 1
NextState <= S4; -- and advance to state-S4
end if;
end case;
end process state_process;
output_latch: process(CLK)
begin
if rising_edge(CLK) then
Z <= Z0;
end if;
end process output_latch;
end Behavior;
And this is the Test Bench code I had written
library ieee;
use ieee.std_logic_1164.ALL;
entity SequenceDetector_8bit_tb is
end SequenceDetector_8bit_tb;
architecture Behavior of SequenceDetector_8bit_tb is
--Input Signal Declaration and initialization
signal CLK : std_logic := '0';
signal X : std_logic := '0';
signal RST : std_logic := '0';
--Output Signal Declaration and initialization
signal Z : std_logic;
constant clk_period: time :=2 ms;
begin
-- instantiate the Unit Under Test (UUT)
mut: entity work.SequenceDetector_8bit
-- using position association
port map(CLK => CLK,
X => X,
RST => RST,
Z => Z);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process clk_process;
stimulus_process: process
begin
-- test sequence
X <= '0';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '0';
wait for clk_period;
X <= '0';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '0';
wait for clk_period;
wait;
end process stimulus_process;
end Behavior;