VHDL process get activated when the sensitivity list isn't changing - vhdl

Question

Process 2 keeps getting activated when there isn't a change. I have a board to test my code, and the state will change when I flip the clock(I set the clock as a button). In my code, the state will only change if I flip Qin. So it isn't doing what I wish it to do, and I spent a lot of time trying to find out what's causing it, but I can't. Please help.
This is the testbench graph TESTBENCH GRAPH
As you can see, in the graph, the output of the PS(present_state) is correct, but in the board, it isn't output right. There is one thing I found that is really important, I tried to output next_state on board, when I flip Qin to '1', the state shows "001", and then I flip clk to '1', the state become "010", which is not suppose to happen. I hope this is an important information.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VendingMechine is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Cr : in STD_LOGIC;
Qin : in STD_LOGIC;
S : in STD_LOGIC;
CB : in STD_LOGIC;
W : in STD_LOGIC;
CRo : out STD_LOGIC_VECTOR(1 DOWNTO 0);
Qo : out STD_LOGIC;
PS : out STD_LOGIC_VECTOR(2 DOWNTO 0);
Wo : out STD_LOGIC;
CBo : out STD_LOGIC;
So : out STD_LOGIC);
end VendingMechine;
architecture Behavioral of VendingMechine is
TYPE state IS(Idle, S1, S2, S3, Soda, Candy, Water);
Signal Next_State : state;
Signal Present_State : state := Idle;
begin
Process1:Process(clk, reset)
begin
if(reset = '1') THEN
Present_State <= Idle;
elsif rising_edge(clk) THEN Present_State <= Next_State;
end if;
end process;
Process2:Process(Qin, Present_State, Cr, S, w)
begin
Next_State <= Present_State;
CRo <= "00"; Qo <= '0'; PS <= "000"; Wo <= '0'; CBo <= '0'; So <= '0';
CASE Present_State IS
When Idle =>
PS <= "000";
if Qin='1' Then Next_State <= S1;
else Next_State <= Idle;
end if;
When S1 =>
PS <= "001";
if Qin='1' Then Next_State <= S2;
elsif Cr = '1' Then Cro <= "01"; Next_State <= Idle;
else Next_State <= S1;
end if;
When S2 =>
PS <= "010";
if Qin='1' Then Next_State <= S3;
elsif Cr = '1' Then CRo <="10"; Next_State <= Idle;
elsif S = '1' Then Next_State <= Soda;
elsif CB = '1' Then Next_State <= Candy;
else Next_State <= S2;
end if;
When S3 =>
PS <= "011";
if Cr = '1' Then CRo <= "11"; Next_State <= Idle;
elsif S = '1' Then Qo <= '1'; Next_State <= Soda;
elsif CB = '1' Then Qo <= '1'; Next_State <= Candy;
elsif W = '1' Then Next_State <= Water;
elsif Qin = '1' Then Qo <= '1';
else Next_State <= S3;
end if;
When Soda =>
PS <= "100";
So <= '1';
Next_State <= Idle;
When Candy =>
PS <= "101";
CBo <= '1';
Next_State <= Idle;
When Water =>
PS <= "110";
Wo <= '1';
Next_State <= Idle;
END CASE;
end process;
end Behavioral;

Answer 1

Process will launch not only when signals changes, but every time you assign something to signal, even if it has same value as before. That may be the reason. In parallel process you can't rely on times launch, but on result in case of some conditions, that came in inputs.

Answer 2

Is Qin connected to an external switch? If yes, you should implement clock-domain synchronization (and possible debouncing) on the inputs.
Please let me know in the comments if you don't know how.
Lack of clock-synchronous signals will cause glitches and thus hang-ups in the state-machine. Lack of debouncing will cause multiple switch pulses ("bouncing")