finite state machine & avoiding metastability - vhdl

Question

I'm trying to do an electronic dice using fsm as well as avoiding metastability in the process. so I've written this code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Dice is
port( clk : in std_logic; -- clock
reset : in std_logic;
key_in : in std_logic; -- key to be preesed to change state
seven_seg : out std_logic_vector (6 downto 0)
);
end Dice;
architecture rulling of Dice is
constant s_one : std_logic_vector (6 downto 0) := "1111001";
constant s_two : std_logic_vector (6 downto 0) := "0100100";
constant s_three : std_logic_vector (6 downto 0) := "0110000";
constant s_four : std_logic_vector (6 downto 0) := "0011001";
constant s_five : std_logic_vector (6 downto 0) := "0010010";
constant s_six : std_logic_vector (6 downto 0) := "0000010";
signal state : std_logic_vector (6 downto 0) := "1111001";
signal Metastable : std_logic;
signal stablee : std_logic;
begin
fsm : process(clk,reset)
begin
if reset = '1' then
--Metastable <= '0';
--stablee <= '0';
--state <= s_one;
seven_seg <= s_one;
else
if rising_edge(clk) then
Metastable <= key_in;
stablee <= Metastable;
case state is
when s_one =>
seven_seg <= s_one; -- writing my OFL (output function logic) what to do inside the state!
if (stablee = '0') then
state <= s_two; -- define my NSL (nest state logic) what conditons there is to change state!
else
state <= s_one;
end if; -- ofl
when s_two =>
seven_seg <= s_two;
if (stablee = '0') then
state <= s_three;
else
state <= s_two;
end if;
when s_three =>
seven_seg <= s_three;
if (stablee = '0') then
state <= s_four;
else
state <= s_three;
end if;
when s_four =>
seven_seg <= s_four;
if (stablee = '0') then
state <= s_five;
else
state <= s_four;
end if;
when s_five =>
seven_seg <= s_five;
if (stablee = '0') then
state <= s_six;
else
state <= s_five;
end if;
when s_six =>
seven_seg <= s_six;
if (stablee = '0') then
state <= s_one;
else
state <= s_six;
end if;
when others =>
state <= s_one;
seven_seg <= s_one;
end case;
end if;
end if;
end process fsm;
end rulling;
for metastability I'm implementing this enter image description here
My question is when i press the debounced button witch is low active for the key_in nothing happens! but when I press the reset button and press key_in its move throw the states. Im really new to VHDL so any help appreciated.