Getting initialized value in the waveform - vhdl

Question

Below is the testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prime_tb is
end prime_tb;
architecture Behavioral of prime_tb is
COMPONENT prime_tb
PORT(
clk : in std_logic;
reset : in std_logic;
seq_in : in std_logic_vector(15 downto 0);
seq_out : out std_logic
);
END COMPONENT;
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal seq_in : std_logic_vector(15 downto 0);
signal seq_out : std_logic;
constant clk_period : time := 10 ns;
begin
uut: prime_tb PORT MAP (
clk => clk,
reset => reset,
seq_in => seq_in,
seq_out => seq_out
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
seq_in <= "0000000011111111";
wait for clk_period;
seq_in <= "0000000000001111";
wait for clk_period;
wait;
end process;
end Behavioral;
I am new to VHDL and I am writing a function that takes a 16-bit input binary value and determining if it is a prime number. The output is '0' or '1'('1' for true and '0' for false). But when I run the simulation, the waveform I got has uninitialized values. It appears that both of my seq_in and seq_out are uninitialized. See link below.
Error:
Can someone help me to fix it?

Answer 1

You have a typo in your UUT instantiation. You didn't mean this:
COMPONENT prime_tb
PORT(
clk : in std_logic;
reset : in std_logic;
seq_in : in std_logic_vector(15 downto 0);
seq_out : out std_logic
);
END COMPONENT;
and this:
uut: prime_tb PORT MAP (
clk => clk,
reset => reset,
seq_in => seq_in,
seq_out => seq_out
);
You meant this:
COMPONENT prime
PORT(
clk : in std_logic;
reset : in std_logic;
seq_in : in std_logic_vector(15 downto 0);
seq_out : out std_logic
);
END COMPONENT;
and this:
uut: prime PORT MAP (
clk => clk,
reset => reset,
seq_in => seq_in,
seq_out => seq_out
);
BTW: you're not driving the reset input to your UUT.