I got the warning "[Synth 8-6014] Unused sequential element MVM_RST_reg was removed. "
I am a little bit confused, because the signal is connected and used
The definition:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.math_real.all;
use work.parameters.all;
entity MVM is
port (
EN: IN std_logic;
DIN: IN signed(DATA_WIDTH_IN-1 downto 0);
WEIGHT: IN signed(DATA_WIDTH_IN -1 downto 0);
CLK: IN std_logic;
RST: IN std_logic;
MVM_RESULT: OUT signed(DATA_WIDTH_IN-1 downto 0):= (OTHERS => '0')
);
end entity MVM;
architecture base of MVM is
begin
process(CLK)
variable acc_value : signed(DATA_WIDTH_IN-1 downto 0):= (OTHERS => '0');
begin
IF rising_edge(CLK) then
IF RST='1' THEN
acc_value := (OTHERS => '0'); -- reset accumulated value to 0
ELSIF EN='1' THEN
acc_value := resize((acc_value + WEIGHT* DIN), DATA_WIDTH_IN);
MVM_RESULT <= acc_value;
END IF;
END IF;
END process;
end base;
My component
component MVM is
port (
EN: in std_logic;
DIN: IN signed(DATA_WIDTH_IN-1 downto 0);
WEIGHT: IN signed(DATA_WIDTH_IN-1 downto 0);
CLK: IN std_logic;
RST: IN std_logic;
MVM_RESULT: OUT signed(DATA_WIDTH_IN-1 downto 0)
);
The signal
signal MVM_RST: std_logic;
My instantiation
MVM_UNITS: MVM
port MAP(
EN => MVM_En,
DIN => DIN_Array(i) ,
Weight => WEIGHT_Array(i),
CLK => CLK,
RST => MVM_RST,
MVM_RESULT => MVM_RESULT_ARRAY(i)
);
the usage of the Reset
state_machine: process(Clk) is
begin
if rising_edge(Clk) then
IF RST='1' then
MVM_RST <= '1';
Else
MVM_RST <= '0';
In detail the warning is reffering to the line RST=> MVM_RST of the instantiation
MVM_RST_reg is removed, because you reset acc_value instead of MVM_RESULT. acc_value is a variable and not a signal. This means, you will only get flipflops for acc_value, if there is a situation were you read acc_value before you assign a value to it. If RST=1, then you assign a value to acc_value but you do not read its value. So no flipflop is needed. If RST=0 and EN=1, then you first assign a value and then read it. So again, no flipflop is needed. As there is no flipflop for acc_value build in, you cannot reset any flipflops by MVM_RST. So the MVM_RST_reg is removed.
Related
I'm trying to make a microprocessor architecture and I'm stuck. My accumulator, IR and PC don't seem to be working and I can't figure out why.
their outputs stay always undefined. I check the mapping and the other components of the mp they're are all correct the problem is somewhere in these registers.
------------------------------------------------------
-- ALU
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity alu is
port ( A, B : in std_logic_vector(15 downto 0);
alufs : in ALU_FCTS;
S : out std_logic_vector( 15 downto 0));
end alu;
architecture arch_alu of alu is
begin
S <= "0000000000000000"; -- sortie par défaut
process(A, B, alufs)
begin
case alufs is
when ALU_B => S <= B;
when ALU_SUB => S <= std_logic_vector(unsigned(B) - unsigned(A));
when ALU_ADD => S <= std_logic_vector(unsigned(B) + unsigned(A));
when ALU_B_INC => S <= std_logic_vector(unsigned(B) + 1);
when ALU_AND => S <= A and B;
when ALU_OR => S <= A or B;
when ALU_XOR => S <= A xor B;
when others => S <= "0000000000000000";
end case;
end process;
end arch_alu;
------------------------------------------------------
-- ACCUMULATER
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity accumulator is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0);
acc15, accz : out std_logic );
end accumulator;
architecture arch_acc of accumulator is
signal q_reg : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then q_reg <= (others => '0');
elsif load='1' then q_reg <= std_logic_vector(unsigned(q_reg) + unsigned(data_in)); end if;
end if;
end process;
data_out <= q_reg;
acc15 <= q_reg(15);
accz <= '1' when q_reg = "0000000000000000";
end arch_acc;
------------------------------------------------------
-- REGISTER PC
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pc_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(11 downto 0) );
end pc_reg;
architecture arch_pc_reg of pc_reg is
signal interne : std_logic_vector(11 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then interne <= (others => '0');
elsif load='1' then interne <= data_in;
end if;
end if;
end process;
data_out <= interne;
end arch_pc_reg;
------------------------------------------------------
-- IR (Instruction Register)
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.up_pack.all;
entity ir_reg is
port( clk, raz, load : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(11 downto 0);
opcode : out OPCODE);
end ir_reg;
architecture arch_ir_reg of ir_reg is
signal interne : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if raz='1' then data_out <= (others => '0');
elsif load='1'
then
data_out <= data_in(11 downto 0);
interne <= data_in(15 downto 12);
end if;
end if;
end process;
opcode <= OP_LDA when interne="0000" else
OP_STO when interne="0001" else
OP_ADD when interne="0010" else
OP_SUB when interne="0011" else
OP_JMP when interne="0100" else
OP_JGE when interne="0101" else
OP_JNE when interne="0110" else
OP_STP when interne="0111" else
OP_AND when interne="1000" else
OP_OR when interne="1001" else
OP_XOR when interne="1010" else
OP_LDR when interne="1011" else
OP_LDI when interne="1100" else
OP_STI when interne="1101" else
OP_JSR when interne="1110" else
OP_RET when interne="1111" else
OP_UNKNOWN;
end arch_ir_reg;
This is not an answer, but a testbench for you to work with. Your accumulator seems to work fine. I tested it with the testbench below. Use it as resource for writing testbenches for the rest of your modules. (You can write a test bench to test all the modules together or individually, just FYI)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_accumulator is
end tb_accumulator;
architecture behav of tb_accumulator is
signal clk : std_logic := '0';
signal raz : std_logic := '1';
signal load : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal data_out : std_logic_vector(15 downto 0) := (others => '0');
signal acc15 : std_logic := '0';
signal accz : std_logic := '0';
begin
--Assign values for signals being passed into accumulator.
clk <= not clk after 2.5 ns;
data_in <= "0000000000000001";
raz <= '0' after 90 ns; --You can do this instead of forcing a signal. Set at what times you want it to change values.
load <= '1' after 100 ns;
accu_inst : entity work.accumulator
port map(
clk => clk,
raz => raz,
load => load,
data_in => data_in,
data_out => data_out,
acc15 => acc15,
accz=> accz
);
end behav;
While all the code is perfectly compiled by ModelSim, I can't simulate it because of "Error loading design"
This is for a CRC encode and decode using a Linear Feedback Shift Register that uses D-FlipFlop as components. So the project is actually composed by the CRC box that contains the LFSR made by DFF.
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC is
generic (
NBit : positive := 64;
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end CRC;
architecture rtl of CRC is
component LFSR
generic (N : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(N-1 downto 0);
ready :out std_logic
);
end component LFSR;
signal input_temp :std_logic_vector(Nbit-1 downto 0);
signal input_LFSR :std_logic;
signal output_LFSR :std_logic_vector(poly-1 downto 0);
signal ready_LFSR :std_logic;
constant crc_check :std_logic_vector(poly-1 downto 0):= (others => '0');
begin
LFSR_o: LFSR generic map (N => poly)
port map(
clk => clk,
reset => reset,
din => input_LFSR,
dout => output_LFSR,
ready => ready_LFSR
);
process (clk)
variable i : natural := 0;
begin
if (md = '1') then
input_temp(Nbit-1 downto poly)<=input(Nbit-1 downto poly);
input_temp(7 downto 0) <=(others =>'0');
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
dout_s <= input(Nbit-1 downto 0) & output_LFSR;
end if;
end if;
elsif(md = '0') then
input_temp(Nbit-1 downto 0)<=input(Nbit-1 downto 0);
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
--codice per il controllo
for t in 0 to poly-1 loop
if (output_LFSR(t)='1') then
dout_r <=(others =>'0');
exit;
elsif(t=poly-1 and output_LFSR(t)='0') then
dout_r <= input(Nbit-1 downto poly);
end if;
end loop;
end if;
end if;
end if;
end process;
end rtl;
here the LFSR
library IEEE;
use IEEE.std_logic_1164.all;
entity LFSR is
generic (NBit : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(Nbit-1 downto 0);
ready :out std_logic
);
end LFSR;
architecture rtl of LFSR is
component DFC
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end component DFC;
signal q_s : std_logic_vector (NBit-1 downto 0):= (others => '0');
signal crc_t : std_logic_vector (NBit-1 downto 0):= (others => '0'); --registro temporaneo su cui fare le operazioni
signal int_0 :std_logic := '0';
signal int_2 :std_logic := '0';
signal int_4 :std_logic := '0';
signal int_8 :std_logic := '0';
begin
int_0<= din xor q_s(7);
int_2<= q_s(1) xor q_s(7);
int_4<= q_s(3) xor q_s(7);
GEN: for i in 0 to Nbit-1 generate
FIRST: if i=0 generate
FF1: DFC port map (
clk => clk,
reset => reset,
d => int_0,
crc => crc_t(i), --funziona benissimo se metto dout(i)
q => q_s(i)
);
end generate FIRST;
THIRD: if i=2 generate
FF2: DFC port map (
clk => clk,
reset => reset,
d => int_2,
crc => crc_t(i),
q => q_s(i)
);
end generate THIRD;
FIFTH: if i=4 generate
FF4: DFC port map (
clk => clk,
reset => reset,
d => int_4,
crc => crc_t(i),
q => q_s(i)
);
end generate FIFTH;
INTERNAL: if i>0 and i<Nbit-1 and i/= 2 and i/=4 generate
FFI: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate INTERNAL;
LAST: if i=Nbit-1 generate
FFN: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate LAST;
end generate GEN;
process(clk)
variable t : natural := 0;
begin
--ready <= '0';
if(rising_edge(clk)) then
t:= t+1;
if t=24 then --per qualche ragione ho bisogno di 3 cicli di clock in più per arrivare al risultato ricercato
dout <= crc_t;
ready <='1';
end if;
end if;
end process;
end rtl;
here the DFF
library IEEE;
use IEEE.std_logic_1164.all;
entity DFC is
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end DFC;
architecture rtl of DFC is
begin
process(clk, reset, d)
begin
if(reset = '1')then
q <= '0';
crc<= '0';
elsif (clk'event and clk='1') then
q <= d;
crc <= d;
end if;
end process;
end rtl;
and finally here the testbench for the CRC
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC_tb is
end CRC_tb;
architecture testbench of CRC_tb is
component CRC is
generic (
NBit : positive := 20; --da rimettere a 64
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end component;
constant T_CLK :time := 25 ns;
constant T_sim :time := 2000 ns;
signal sim_time :std_logic :='1';
constant M :integer :=20; --da rimettere a 64, Nbit
constant N :integer :=8; -- poly
signal clk_tb :std_logic :='0';
signal reset_tb :std_logic :='1';
signal md_tb :std_logic;
signal input_tb :std_logic_vector(M-1 downto 0);
signal dout_s_tb :std_logic_vector(M-1 downto 0);
signal dout_r_tb :std_logic_vector(M-N-1 downto 0);
begin
clk_tb <= (not(clk_tb)and sim_time) after T_CLK/2;
sim_time <= '0' after T_sim;
DUT_i : CRC
generic map (
Nbit => M,
poly => N
)
port map (
clk => clk_tb,
reset => reset_tb,
md => md_tb,
input => input_tb,
dout_s => dout_s_tb,
dout_r => dout_r_tb
);
input_process : process(clk_tb)
begin
if(rising_edge(clk_tb)) then
md_tb <= '1';
input_tb <= "10100111010000000000";
end if;
end process input_process;
end testbench;
I was expecting that everything went fine given that the CRC code doesn't do much if not creating connections. I'm very new to VHDL so I can't understand very well what
** Error: (vsim-3733) C:/Modeltech_pe_edu_10.4a/CRC2.0/CRC.vhd(50):
No default binding for component instance 'LFSR_o'.
The following component generic is not on the entity: N Time: 0 ns
Iteration: 0 Instance: /crc_tb/DUT_i/LFSR_o File:
C:/Modeltech_pe_edu_10.4a/CRC2.0/LFSR.vhd
Loading work.dfc(rtl)
Error loading design
means.
Thanks all for the answers.
I am implementing a multiplier in which i multiply A (8 bits) and B (8 bits), and store result at S. Number of bit required for output S is 16 bits. S have higher part SH and lower part SL.Every time i shift ,add operation is performed
i am getting following errors in my controller part :-
Attribute event requires a static signal prefix
is not declared.
"**" expects 2 arguments
and my code is:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PIPO is
port (reset: in std_logic ;
B:IN STD_LOGIC_VECTOR (7 downto 0 );
LOAD:in std_logic ;
SHIFT:in std_logic ;
ADD:in std_logic ;
Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
C_out:in std_logic ;
CLK:in std_logic ;
result: out STD_LOGIC_VECTOR (15 downto 0) ;
LSB:out std_logic ;
TB:out std_logic_vector (7 downto 0) );
end ;
architecture rtl OF PIPO is
signal temp1 : std_logic_vector(15 downto 0);
----temp2 -add
signal temp2 : std_logic ;
begin
process (CLK, reset)
begin
if reset='0' then
temp1<= (others =>'0');
temp2<= '0';
elsif (CLK'event and CLK='1') then
if LOAD ='1' then
temp1(7 downto 0) <= B;
temp1(15 downto 8) <= (others => '0');
end if ;
if ADD= '1' then
temp2 <='1';
end if;
if SHIFT= '1' then
if ADD= '1' then
------adder result ko add n shift
temp2<= '0';
temp1<=C_out & Sum & temp1( 7 downto 1 );
else
----only shift
temp1<= '0' & temp1( 15 downto 1 );
end if;
end if;
end if;
end process;
LSB <=temp1(0);
result<=temp1( 15 downto 0 );
TB <=temp1(15 downto 8);
end architecture rtl;
-------------------------------------------
-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Controller is
Port ( ADD :OUT STD_LOGIC;
SHIFT:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC;
STOP:OUT STD_LOGIC;
STRT:IN STD_LOGIC;
LSB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
reset:IN STD_LOGIC );
end ;
architecture rtl OF Contoller is
---RTL level code is inherently synchronous
signal count : unsigned (2 downto 0);
----differnt states
type state_typ is ( IDLE, INIT, TEST, ADDs, SHIFTs );
signal state : state_typ;
begin
--controller : process (ADD,SHIFT,LOAD,STOP,STRT,LSB,CLK,reset)
process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)
begin
if reset='0' then
state <= IDLE;
count <= "000";
elsif (CLK'event and CLK='1') then
case state is
when IDLE =>
if STRT = '1' then
--- if STRT = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if LSB = '0' then
state <= SHIFTs;
else
state <= ADDs;
end if;
when ADDs =>
state <= SHIFTs;
when SHIFTs =>
if count = "111" then
count <= "000";
state <= IDLE;
else
count<= std_logic_vector(unsigned(count) + 1);
state <= TEST;
end if;
end case;
end if;
end process ;
STOP <= '1' when state = IDLE else '0';
ADD <= '1' when state = ADDs else '0';
SHIFT <= '1' when state = SHIFTs else '0';
LOAD <= '1' when state = INIT else '0';
end architecture rtl;
----------------------------------------------
--------------------------------------------
---multiplicand
library ieee;
use ieee.std_logic_1164.all;
entity multiplicand is
port (A : in std_logic(7 downto 0);
reset :in std_logic;
LOAD : in std_logic;
TA : OUT STD_LOGIC(7 downto 0);
CLK : in std_logic );
end entity;
architecture rtl OF multiplicand is
begin
process (CLK, reset)
begin
if reset='0' then
TA <= (others =>'0'); -- initialize
elsif (CLK'event and CLK='1') then
if LOAD_cmd = '1' then
TA(7 downto 0) <= A_in; -- load B_in into register
end if;
end if ;
end process;
end architecture rtl;
------------------------------------------------------
------------------------------------------------------
---Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port (A : in std_logic;
B : in std_logic;
C_in : in std_logic;
Sum : out std_logic ;
C_out : out std_logic);
end;
architecture struc of Full_Adder is
begin
Sum <= A xor B xor C_in;
C_out <= (A and B) or (A and C_in) or (B and C_in);
end struc;
------------------------------------------------------------
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
Port ( TA : in STD_LOGIC_VECTOR (7 downto 0);
TB : in STD_LOGIC_VECTOR (7 downto 0);
Sum : out STD_LOGIC_VECTOR (7 downto 0);
C_in : in STD_LOGIC;
C_out : out STD_LOGIC);
end Adder;
architecture struc of Adder is
component Full_Adder is
port(A : in std_logic;
B : in std_logic;
C_in : in std_logic;
Sum : out std_logic ;
C_out : out std_logic);
end component;
signal C: std_logic_vector (7 downto 0);
begin
FA0:Full_Adder port map(TA(0), TB(0), C_in, Sum(0), C(0));
FA1: Full_Adder port map(TA(1), TB(1), C(0), Sum(1), C(1));
FA3: Full_Adder port map(TA(2),TB(2), C(1), Sum(2), C(2));
FA4: Full_Adder port map(TA(3), TB(3), C(2), Sum(3), C(3));
FA5: Full_Adder port map(TA(4), TB(4), C(3), Sum(4), C(4));
FA6: Full_Adder port map(TA(5), TB(5), C(4), Sum(5), C(5));
FA7: Full_Adder port map(TA(6), TB(6), C(5), Sum(6), C(6));
FA8: Full_Adder port map(TA(7), TB(7), C(6), Sum(7), C(7));
C_out <= C(7);
end struc;
------------------------------------------------------------
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
Port ( num1 : in STD_LOGIC_VECTOR (7 downto 0);
num2 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0);
CLK:in std_logic ;
reset:IN STD_LOGIC;
STRT:IN STD_LOGIC;
STOP:OUT STD_LOGIC );
end multiplier;
architecture rtl of Multiplier is
signal ADD :STD_LOGIC;
signal SHIFT :STD_LOGIC;
signal LOAD :STD_LOGIC;
signal LSB :STD_LOGIC;
signal A : STD_LOGIC_VECTOR (7 downto 0);
signal B :STD_LOGIC_VECTOR (7 downto 0);
signal Sum:STD_LOGIC_VECTOR (7 downto 0);
signal C_out:STD_LOGIC;
component Controller
port (
ADD :OUT STD_LOGIC;
SHIFT:OUT STD_LOGIC;
LOAD:OUT STD_LOGIC;
STOP:OUT STD_LOGIC;
STRT:IN STD_LOGIC;
LSB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
reset:IN STD_LOGIC );
end component;
component Adder
port (
TA : in STD_LOGIC_VECTOR (7 downto 0);
TB : in STD_LOGIC_VECTOR (7 downto 0);
Sum : out STD_LOGIC_VECTOR (7 downto 0);
C_in : in STD_LOGIC;
C_out : out STD_LOGIC);
end component;
component PIPO
port (reset: in std_logic ;
B:IN STD_LOGIC_VECTOR (7 downto 0 );
LOAD:in std_logic ;
SHIFT:in std_logic ;
ADD:in std_logic ;
Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
C_out:in std_logic ;
CLK:in std_logic ;
result: out STD_LOGIC_VECTOR (15 downto 0) ;
LSB:out std_logic ;
TB:out std_logic );
end component;
component multiplicand
port (A : in std_logic (7 downto 0);
reset :in std_logic;
LOAD : in std_logic;
TA : OUT STD_LOGIC(7 downto 0);
CLK : in std_logic );
end component ;
begin
inst_Controller: Controller
port map (ADD => ADD,
SHIFT =>SHIFT,
LOAD =>LOAD ,
STOP =>STOP,
STRT =>STRT,
LSB =>LSB ,
CLK =>CLK ,
reset =>reset
);
inst_multiplicand :multiplicand
port map (A =>A,
reset=>reset,
LOAD =>LOAD,
TA => TA(7 downto 0),
CLK => CLK
);
inst_PIPO :PIPO
port map ( reset => reset,
B => B ,
LOAD =>LOAD,
SHIFT=>SHIFT,
ADD=>ADD,
Sum=>Sum,
C_out=>C_out,
CLK=>CLK,
result=>result,
LSB=>LSB,
TB=>TB
);
inst_Full_Adder : Full_Adder
port map ( TA => TA,
TB =>TB,
Sum=>Sum ,
C_in=>C_in,
C_out=>C_out
);
end rtl;
Actually the space between CLK and the apostrophe/tick isn't significant
david_koontz#Macbook: token_test
elsif (CLK 'event and CLK ='1') then
KEYWD_ELSIF (151) elsif
DELIM_LEFT_PAREN ( 9) (
IDENTIFIER_TOKEN (128) CLK
DELIM_APOSTROPHE ( 8) '
IDENTIFIER_TOKEN (128) event
KEYWD_AND (134) and
IDENTIFIER_TOKEN (128) CLK
DELIM_EQUAL ( 25) =
CHAR_LIT_TOKEN ( 2) '1'
DELIM_RIGHT_PAREN ( 10) )
KEYWD_THEN (211) then
gives the same answer as:
david_koontz#Macbook: token_test
elsif (CLK'event and CLK ='1') then
KEYWD_ELSIF (151) elsif
DELIM_LEFT_PAREN ( 9) (
IDENTIFIER_TOKEN (128) CLK
DELIM_APOSTROPHE ( 8) '
IDENTIFIER_TOKEN (128) event
KEYWD_AND (134) and
IDENTIFIER_TOKEN (128) CLK
DELIM_EQUAL ( 25) =
CHAR_LIT_TOKEN ( 2) '1'
DELIM_RIGHT_PAREN ( 10) )
KEYWD_THEN (211) then
In vhdl, there is no lexical element parsing requiring a lack of white space. (Sorry Russel).
Correcting the other syntax ambiguities of your code (see below, missing context clause, Controller misspelled in the architecture declaration, count used as both a scalar and array subtype), results in two different VHDL analyzers swallowing the space between CLK and ' just fine.
The problem is in the tool you are using not actually being standard compliant or the code you present as having the problem isn't actually representational of the code generating the error. If a non-compliant tool it's likely a shortcoming you can live with, although there may be more things a bit more irksome.
david_koontz#Macbook: ghdl -a controller.vhdl
david_koontz#Macbook: nvc -a controller.vhdl
david_koontz#Macbook:
(no errors, it also elaborates without a test bench in ghdl, nvc disallows top level ports - which it is permitted to do by the standard)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Controller is
Port (
ADD: OUT STD_LOGIC;
SHIFT: OUT STD_LOGIC;
LOAD: OUT STD_LOGIC;
STOP: OUT STD_LOGIC;
STRT: IN STD_LOGIC;
LSB: IN STD_LOGIC;
CLK: IN STD_LOGIC;
reset: IN STD_LOGIC
);
end entity;
architecture rtl OF Controller is
---RTL level code is inherently synchronous
signal count : std_logic_vector (2 downto 0);
----differnt states
type state_typ is ( IDLE, INIT, TEST, ADDs, SHIFTs );
signal state : state_typ;
begin
NOLABEL:
process (CLK, reset)
begin
if reset='0' then
state <= IDLE;
count <= "000";
elsif (CLK 'event and CLK ='1') then
case state is
when IDLE =>
if STRT = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if LSB = '0' then
state <= SHIFTs;
else
state <= ADDs;
end if;
when ADDs =>
state <= SHIFTs;
when SHIFTs =>
if count = "111" then -- verify if finished
count <= "000"; -- re-initialize counter
state <= IDLE; -- ready for next multiply
else
count <= -- increment counter
std_logic_vector(unsigned(count) + 1);
state <= TEST;
end if;
end case;
end if;
end process;
---end generate; ???
STOP <= '1' when state = IDLE else '0';
ADD <= '1' when state = ADDs else '0';
SHIFT <= '1' when state = SHIFTs else '0';
LOAD <= '1' when state = INIT else '0';
end architecture rtl;
The error message appears to stem from the signal CLK (the prefix for the event attribtute). There is no other use of the event attribute in your code presented with the question. A signal is one of the elements of entity_class that can be decorated with an attribute.
In the VHDL LRM's section on predefined attributes 'EVENT can only decorate a signal, and CLK is a signal (declared in a port). In that section the prefix is required to be denoted by a static signal name.
Is CLK a static signal name? Yes it is. It's a scalar subtype declared in the entity declaration and is locally static (available at analysis time - it's a scalar, a simple name and not involving a generic).
And about now you might get why someone would wonder if the code in the question is representational of the code generating the error or the VHDL tool used is not compliant.
The error message you report is usually associated with trying to use 'EVENT with an indexed signal name, e.g. w(i)'event. (See Signal attributes on a signal vector).
You're going to kick yourself for this one:
elsif (CLK 'event and CLK ='1') then
Should be:
elsif (CLK'event and CLK ='1') then
See the difference?
Even better:
elsif rising_edge(CLK) then
It seems you're missing a clk entry in the process
Change the line reading:
process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)
to read:
process (clk, reset)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,MCM3);
dff2 : DFF port map(Q2,Clk,add_out1);
dff3 : DFF port map(Q3,Clk,add_out2);
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out3;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(`
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
process(Clk)
begin
if ( rising_edge(Clk) ) then
qt <= D;
end if;
end process;
end Behavioral;
When I run this code it compiles successfully error free syntax but I get several warning and because of that I am not getting desired result. I get Xin, Clkin & Yout undefined in simulation result. I tried in different ways but still I haven't resolved these warnings:
1) WARNING:Xst:1293 - FF/Latch has a constant value of 0 in
block . This FF/Latch will be trimmed during the optimization
process.
2) WARNING:Xst:1293 - FF/Latch has a constant value of
0 in block . This FF/Latch will be trimmed during the
optimization process.
3) WARNING:Xst:1293 - FF/Latch has a
constant value of 0 in block . This FF/Latch will be trimmed
during the optimization process.
4) WARNING:Xst:1896 - Due to other
FF/Latch trimming, FF/Latch has a constant value of 0 in
block . This FF/Latch will be trimmed during
There seems to be no problem with the code. The only thing that I thought could go wrong is the fact that the fir module doesn't have any reset. The code for fir is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
reset: in std_logic;
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal yout_int : signed(15 downto 0);
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,reset,MCM3);
dff2 : DFF port map(Q2,Clk,reset,add_out1);
dff3 : DFF port map(Q3,Clk,reset,add_out2);
--an output produced at every positive edge of clock cycle.
registered_yout: process
begin
wait until rising_edge(clk);
if (reset = '1') then
yout_int <= (others => '0');
else
yout_int <= add_out3;
end if;
end process;
Yout <= yout_int;
end Behavioral;
I also added in reset for dff and the changed file looks like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
registered_qt : process
begin
wait until rising_edge(clk);
if (reset = '1') then
qt <= (others => '0');
else
qt <= D;
end if;
end process;
end Behavioral;
The testbench that I used is as follows:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tb is
end entity tb;
architecture test_bench of tb is
component fir_123 is
port( Clk : in std_logic;
reset : in std_logic;
Xin : in signed(7 downto 0);
Yout : out signed(15 downto 0)
);
end component fir_123;
constant clk_per : time := 8 ns;
signal clk: std_logic;
signal reset: std_logic;
signal Xin : signed(7 downto 0);
signal Yout : signed(15 downto 0);
begin
dft : component fir_123
port map (
Clk => clk,
reset => reset,
Xin => Xin,
Yout => Yout
);
Clk_generate : process --Process to generate the clk
begin
clk <= '0';
wait for clk_per/2;
clk <= '1';
wait for clk_per/2;
end process;
Rst_generate : process --Process to generate the reset in the beginning
begin
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait;
end process;
Test: process
begin
Xin <= (others => '0');
wait until rising_edge(clk);
Xin <= (others => '1');
wait until rising_edge(clk);
Xin <= (others => '0');
wait for clk_per*10;
report "testbench finished" severity failure;
end process test;
end architecture test_bench;
I have checked the waveforms in a simulator and they all seem to be defined after the reset has been deasserted. The fact that Xin and Clk is undefined shows that there is something wrong with the testbench.
I am designing a simple combination lock design in VHDL on a Spartan 6 FPGA. This error has come up and i am a bit confused to how i could fix it. I have "googled" this and according to this answer in this thread Too many comps of type “BUFGMUX” found to fit this deviceI beleive i know the problem but i am unsure how to solve it.
Now correct me if i am wrong but i believe this error came about due to the following code in my design
--clock divider
process(cclk,clr)
begin
if (clr ='1') then
Count200Hz <= X"00000";
--clk200 <= '0';
temp <= '0';
elsif rising_edge(cclk) then
if (Count200Hz = clk200HzEndVal) then
clk200 <= not temp;
Count200Hz <= X"00000";
else
Count200Hz <= Count200Hz + '1';
end if;
end if;
end process;
-- 2-bit counter
process(cclk,clr)
begin
if clr = '1' then
s <= "00";
elsif rising_edge(cclk) then
s <= s+1;
end if;
end process;
--state machine
state_mach:PROCESS(lclk, clr)
BEGIN
IF clr = '1' THEN
present_state <= idle;
ELSIF rising_edge(lclk) THEN
present_state <= next_state;
end if;
END PROCESS;
pulse_process: process(cclk, rst)
begin
if rst = '0' then
pulse <= '0';
count <= 0;
current_state <= idle;
elsif (rising_edge(cclk))then
current_state <= next_state;
....
These code are from different vhdl modules in my design.
does the ise believes that there are three different clock used in my design hence why the error is thrown??
The thing is that they are different clock but they stem from the systems clock ones the clock at an lower frequency, one is the clock pulse.
I have added my top-level design for some clarity
Any help is appreciated
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity simpleLock_top is
Port (
mclk : in STD_LOGIC;
rst : in STD_LOGIC;
btnl : in STD_LOGIC;
btnr : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (3 downto 0);
seg7 : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 DOWNTO 0);
dp : out STD_LOGIC);
end simpleLock_top;
architecture Behavioral of simpleLock_top is
component x7seg_msg is
Port (
x : in STD_LOGIC_VECTOR (15 downto 0);
cclk : in STD_LOGIC;
clr : in STD_LOGIC;
seg7 : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
dp : out STD_LOGIC);
end component;
component clkdiv is
Port (
cclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk200 : out STD_LOGIC);
end component;
component simpleLock is
PORT (
lclk : IN STD_LOGIC;
clr : IN STD_LOGIC;
btnl : IN STD_LOGIC;
btnr : IN STD_LOGIC;
code : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
digit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
user_input : OUT STD_LOGIC_VECTOR(15 downto 0));
end component;
component clock_pulse is
PORT (
cclk : IN STD_LOGIC;
rst : IN STD_LOGIC;
trig : IN STD_LOGIC;
pulse : OUT STD_LOGIC);
end component;
constant code : STD_LOGIC_VECTOR(15 downto 0):= X"1234";
signal digit: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal user_input : std_logic_vector(15 downto 0);
signal clk200, clkp, btn01: STD_LOGIC;
signal btn : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
btn(0) <= btnr;
btn(1) <= btnl;
btn01 <= btn(0) or btn(1);
--led <= X"00";
V1: clkdiv
port map(
cclk => mclk,
clr => rst,
clk200 => clk200);
V2: x7seg_msg
port map(
x => user_input,
cclk => clk200,
clr => rst,
seg7 => seg7,
an => an,
dp => dp );
V3: simpleLock
port map(
lclk => clkp,
clr => rst,
btnl => btnl,
btnr => btnr,
code => code,
sw => sw,
led => led,
digit => digit,
user_input => user_input);
V4: clock_pulse
port map(
cclk => clk200,
rst => rst,
trig => btn01,
pulse => clkp);
end Behavioral;
Clock Enable
In an FPGA design, it is often better to use the less possible different clocks.
If your "clock_pulse" module generate a one cycle clock pulse, don't use this pulse as a clock ('clkp' in your code), but as a clock enable ('enable' in the code below).
myproc : process(clk, rst)
begin
if rst = '1' THEN
-- your asynchronously reseted signals
elsif rising_edge(clk) THEN
if enable = '1' then
-- things that must be done when you get the one cycle pulse
end if;
end if;
end process;
But take care of any unmanaged clock domain crossing...
Hope this helps.