Shift Right Register-ParallelLoad - vhdl

Question

I have to create an n bit shift right register(used 4 bits here) with parallel load. For this purpose i used a Mux 2 in 1 and d flip flops. If load is '1' then the register is loaded with a value(DataIn), otherwise the register starts to shift.
The code for the Multiplexer is:
entity Mux2in1onebit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC;
sel : in STD_LOGIC);
end Mux2in1onebit;
architecture Behavioral of Mux2in1onebit is
begin
Q <= A when sel = '0' else
B;
end Behavioral
The code for the flip flop:
entity FlipFlop is
Port ( Din : in STD_LOGIC;
Q : out STD_LOGIC;
Enable : in STD_LOGIC;
Clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end FlipFlop;
architecture Behavioral of FlipFlop is
signal Qtemp : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset = '1') then
Qtemp <= '0';
else
if (enable = '1') then
Qtemp <= Din;
else
Qtemp <= Qtemp;
end if;
end if;
end if;
end process ;
Q <= Qtemp;
end Behavioral;
Now in a top level module i have connected the muxs and the flip flops as following:
entity ShiftRegister is
Port ( DataIn : in STD_LOGIC_VECTOR (3 downto 0);
DataOut : out STD_LOGIC_VECTOR (3 downto 0);
Enable : in STD_LOGIC;
Load :in STD_LOGIC;
BitIn : in STD_LOGIC;
Bitout : out STD_LOGIC;
Reset : in STD_LOGIC;
Clk : in STD_LOGIC);
end ShiftRegister;
architecture Structural of ShiftRegister is
COMPONENT FlipFlop
PORT(
Din : IN std_logic;
Enable : IN std_logic;
Clk : IN std_logic;
Reset : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
COMPONENT Mux2in1onebit
PORT(
A : IN std_logic;
B : IN std_logic;
sel : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
signal sigdin, sigq : std_logic_vector(3 downto 0);
begin
MBIT3: Mux2in1onebit PORT MAP(
A => BitIn,
B => DataIn(3),
Q => sigdin(3),
sel => Load
);
BIT3: FlipFlop PORT MAP(
Din => sigdin(3),
Q => sigq(3),
Enable => Enable,
Clk => Clk,
Reset => Reset
);
MBIT2: Mux2in1onebit PORT MAP(
A => sigq(3),
B => DataIn(2),
Q => sigdin(2),
sel => Load
);
BIT2: FlipFlop PORT MAP(
Din => sigdin(2),
Q => sigq(2),
Enable => Enable,
Clk => Clk,
Reset => Reset
);
MBIT1: Mux2in1onebit PORT MAP(
A => sigq(2),
B => DataIn(1),
Q => sigdin(1),
sel => Load
);
BIT1: FlipFlop PORT MAP(
Din => sigdin(1),
Q => sigq(1),
Enable => Enable,
Clk => Clk,
Reset => Reset
);
MBIT0: Mux2in1onebit PORT MAP(
A => sigq(1),
B => DataIn(0),
Q => sigdin(0),
sel => Load
);
BIT0: FlipFlop PORT MAP(
Din => sigdin(0),
Q => sigq(0),
Enable => Enable,
Clk => Clk,
Reset => Reset
);
BitOut <= sigq(0);
DataOut <= sigdin;
end Structural;
Now when i simulate the above code, for reset = '1' the flip flops are set to 0 and when load = '1' then the DataIn is loaded, as expected. But when enable = '1' the register does not shift, but i get "0000" as a result. Thanks.

Answer 1

Your question isn't quite a Minimal, Complete, and Verifiable example, missing the stimuli and actual results.
All three entity and architecture pairs were missing context clauses (library ieee; use ieee.std_logic_1164.all;) and the architecture for Mux2in1onebit was missing a semicolon after end Behavioral.
After fixing those I wrote a simple testbench:
library ieee;
use ieee.std_logic_1164.all;
entity sr_tb is
end entity;
architecture fum of sr_tb is
signal datain: std_logic_vector (3 downto 0) := "1011"; -- load value
signal dataout: std_logic_vector (3 downto 0);
signal enable: std_logic := '0';
signal load: std_logic := '0';
signal bitin: std_logic;
signal bitout: std_logic;
signal reset: std_logic := '0';
signal clk: std_logic := '0';
begin
DUT:
entity work.shiftregister
port map (
datain => datain,
dataout => dataout,
enable => enable,
load => load,
bitin => bitin,
bitout => bitout,
reset => reset,
clk => clk
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if now > 160 ns then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 6 ns;
reset <= '0';
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 10 ns;
load <= '1';
enable <= '1';
wait for 10 ns;
load <= '0';
enable <= '0';
wait for 10 ns;
bitin <= '0';
wait for 10 ns;
enable <= '1';
wait for 10 ns;
bitin <= '1';
wait for 10 ns;
bitin <= '0';
wait for 10 ns;
wait for 10 ns;
bitin <= '1';
wait for 10 ns;
wait;
end process;
end architecture;
And that produced:
Which shows sigq outputs of the four flip flops are correct and points out DataOut should be assigned from sigq instead of sigdin:
dataout <= sigdin; -- should be sigq
end architecture structural;
If you follow sigq(0) in the waveform you'll see it's values are consisted with the stimuli.
From your comment to your question you were also missing Enable being a '1' when loading.