Quartus Prime Lite Failed to find INSTANCE - vhdl

Question

I've tryed to run a simulation with ModelSim on Quartus Prime Lite but I've got this error messages:
Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1'.
Error (suppressible): (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1'
It doesn't matter which code I'm running. The compilation was succesfull and the simulation path is right.
-- The code.
-- ADC reader: reads data from ADXL345
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity g_reader is port (
clk_50: in std_logic; -- 50 MHz clock
reset_n : in std_logic; -- reset signal (active low)
-- SPI interface
CS_N : out std_logic; -- connected to chip select of g sensor
SCLK : out std_logic; -- spi clock
SDIO : inout std_logic; -- spi data (bidirectional)
-- data output
dataX : out std_logic_vector(12 downto 0);
dataY : out std_logic_vector(12 downto 0);
dataZ : out std_logic_vector(12 downto 0)
);
end g_reader;
architecture behavior of g_reader is
signal SCLK_counter : integer := 0; -- starts clock
signal SCLK_1 : std_logic; -- 1 MHz clock
constant half_period : time := 10 ns;
begin
-- SCLK
process(clk_50)
begin
if (falling_edge(clk_50)) then
if (SCLK_counter <= 24) then
SCLK_1 <= '0';
else
SCLK_1 <= '1';
end if;
if (SCLK_counter >= 49) then
SCLK_counter <= 0;
else
SCLK_counter <= SCLK_counter + 1;
end if;
end if;
end process;
CS_N <= '0';
SCLK <= '0';
dataX <= "0000000000000";
dataY <= "0000000000000";
dataZ <= "0000000000000";
end behavior;
The testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY g_reader_vhd_tst IS
END g_reader_vhd_tst;
ARCHITECTURE g_reader_arch OF g_reader_vhd_tst IS
-- constants
constant half_period : time := 10 ns;
-- signals
signal clk : std_logic := '0';
SIGNAL clk_50 : STD_LOGIC;
SIGNAL CS_N : STD_LOGIC;
SIGNAL dataX : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL dataY : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL dataZ : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL reset_n : STD_LOGIC;
SIGNAL SCLK : STD_LOGIC;
SIGNAL SDIO : STD_LOGIC;
COMPONENT g_reader
PORT (
clk_50 : IN STD_LOGIC;
CS_N : OUT STD_LOGIC;
dataX : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
dataY : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
dataZ : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
reset_n : IN STD_LOGIC;
SCLK : OUT STD_LOGIC;
SDIO : INOUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : g_reader
PORT MAP (
-- list connections between master ports and signals
clk_50 => clk_50,
CS_N => CS_N,
dataX => dataX,
dataY => dataY,
dataZ => dataZ,
reset_n => reset_n,
SCLK => SCLK,
SDIO => SDIO
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
clk_proc : process
begin
clk <= not clk after half_period;
end process clk_proc;
end g_reader_arch;