I'm learning PL/SQL and I can not find the error
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ORA-06550: line 52, column 5: PLS-00103: Encountered the symbol "END"
when expecting one of the following:
& = - + ; < / > at in is mod remainder not rem <> or != or ~= >= <= <> and or like like2 like4 likec between
|| member submultiset The symbol ";" was substituted for "END" to
continue.
This is the code:
DECLARE
N_SUC NUMBER;
N_CLIENTE NUMBER;
N_TVENTA NUMBER;
N_FECHA DATE;
I_CLIENTE NUMBER;
I_TVENTA NUMBER;
begin
N_SUC := 1;
N_CLIENTE :=1;
N_TVENTA :=1;
I_CLIENTE :=1;
I_TVENTA := 1;
for loop_one in 1..4
loop
FOR LOOP_two IN 1..25
LOOP
IF N_TVENTA > 75 THEN
I_TVENTA:= I_TVENTA + 1;
END IF;
if N_CLIENTE <=10 then
I_CLIENTE:= 1;
elsif N_CLIENTE >10 AND N_CLIENTE <= 20 then
I_CLIENTE:= 2;
elsif N_CLIENTE>20 AND N_CLIENTE <= 30 THEN
I_CLIENTE:= 3;
elsif N_CLIENTE>30 AND N_CLIENTE <= 40 then
I_CLIENTE:= 4;
elsif N_CLIENTE>40 AND N_CLIENTE <= 50 then
I_CLIENTE:= 5;
elsif N_CLIENTE>50 AND N_CLIENTE <= 60 then
I_CLIENTE:= 6;
elsif N_CLIENTE>60 AND N_CLIENTE <= 70 then
I_CLIENTE:= 7;
elsif N_CLIENTE>70 AND N_CLIENTE <= 80 then
I_CLIENTE:= 8;
elsif N_CLIENTE>80 AND N_CLIENTE <= 90 then
I_CLIENTE:= 9;
elsif N_CLIENTE>90 AND N_CLIENTE <= 100 then
I_CLIENTE:= 10;
end if;
SELECT SYSDATE into N_FECHA FROM dual;
INSERT INTO marcos.VENTA
VALUES(SEQ_VENTA.nextval, 0, N_FECHA|| '-'||SEQ_VENTA, N_SUC, I_CLIENTE, I_TVENTA);
N_CLIENTE:= N_CLIENTE+1;
N_TVENTA:=N_TVENTA+1
END LOOP;
N_SUC := N_SUC+ 1;
end loop ;
commit;
EXCEPTION
WHEN OTHERS THEN
dbms_output.put_line('Se ha producido un error') ;
rollback;
end;
You miss a line terminator (semi-colon) in line 51, here:
N_TVENTA:=N_TVENTA+1
Related
I am a freshman to VHDL, and am learning it by myself.
As a practice, I am doing a data process (calculate spatial average data) to a 320*240 graphic data.
I am considering the way like this :
1. Create a 10*10 cluster of homogeneous simple elements, where each element calculates the average value of a single pixel.
2. Each time connect one portion of the graphic data to the 10*10 cluster, make calculation then change connection. And after 32*24 times of operation, the work is finished.
But I got synthesizing problem in step 2. In order to dynamically change connections, I have to use variables other than i,j in FOR statement. But it seems to be not synthesizable for this pattern of using FOR loop(the synthesizing time goes unlimited.).
Would anyone help me out of this?
The problematic code segment is as follows:
FSM1: process(clk) is
variable cnt1 : integer range 0 to 5 := 0;
variable cnt2 : integer range 0 to 32-1 := 0;
variable cnt3 : integer range 0 to 24-1 := 0;
variable BlockBaseX : integer range 0 to 310 := 0;
variable BlockBaseY : integer range 0 to 230 := 0;
variable varPRLLc_ave_indata : std_logic_vector(400*8-1 downto 0) :=(others=>'0');
begin
if rising_edge(clk) then
PRLLc_ave_indata <= varPRLLc_ave_indata;
if stateFSM2A = s3 then
case stateFSM1 is
when s1 =>
if do_InitCopy = '1' then
workGD <= baseGD;
end if;
stateFSM1 <= s2;
when s2 =>
if do_NumProc = '1' then
case cnt1 is
when 0 =>
BlockBaseX := cnt2*10; -- 10, 20, ..., 310
BlockBaseY := cnt3*10; -- 10, 20, ..., 230
for i in 0 to 9 loop
for j in 0 to 9 loop -- PRLLc_ave_indata (400*8-1 downto 0);
if i = 9 then
if j = 9 then
varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(BlockBaseY+i, BlockBaseX+j) & workGD(BlockBaseY+i, BlockBaseX+j-1) & workGD(BlockBaseY+i-1, BlockBaseX+j) & workGD(BlockBaseY+i-1, BlockBaseX+j-1);
else
varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(BlockBaseY+i, BlockBaseX+j) & workGD(BlockBaseY+i, BlockBaseX+j+1) & workGD(BlockBaseY+i-1, BlockBaseX+j) & workGD(BlockBaseY+i-1, BlockBaseX+j+1);
end if;
else
if j = 9 then
varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(BlockBaseY+i, BlockBaseX+j) & workGD(BlockBaseY+i, BlockBaseX+j-1) & workGD(BlockBaseY+i+1, BlockBaseX+j) & workGD(BlockBaseY+i+1, BlockBaseX+j-1);
else
varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(BlockBaseY+i, BlockBaseX+j) & workGD(BlockBaseY+i, BlockBaseX+j+1) & workGD(BlockBaseY+i+1, BlockBaseX+j) & workGD(BlockBaseY+i+1, BlockBaseX+j+1);
end if;
end if;
end loop;
end loop;
-- If the above For loop is replaced with the following one(BlockBaseX,BlockBaseY are removed), the synthesis can be accomplished.
-- for i in 0 to 9 loop
-- for j in 0 to 9 loop -- PRLLc_ave_indata (400*8-1 downto 0);
-- if i = 9 then
-- if j = 9 then
-- varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(i, j) & workGD(i, j-1) & workGD(i-1, j) & workGD(i-1, j-1);
-- else
-- varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(i, j) & workGD(i, j+1) & workGD(i-1, j) & workGD(i-1, j+1);
-- end if;
-- else
-- if j = 9 then
-- varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(i, j) & workGD(i, j-1) & workGD(i+1, j) & workGD(i+1, j-1);
-- else
-- varPRLLc_ave_indata((i*10+j)*32+31 downto (i*10+j)*32) := workGD(i, j) & workGD(i, j+1) & workGD(i+1, j) & workGD(i+1, j+1);
-- end if;
-- end if;
-- end loop;
-- end loop;
when 1 =>
when 2 =>
when 3 => -- got answer
when 4 =>
when others =>
end case;
if cnt1 < 5 then
cnt1 := cnt1 + 1;
else
cnt1 := 0;
if cnt2 < 32 then
cnt2 := cnt2 + 1;
else
cnt2 := 0;
if cnt3 < 24 then
cnt3 := cnt3 + 1;
else
cnt3 := 0;
stateFSM1 <= s3;
end if;
end if;
end if;
else
end if;
when s3 => -- after detecting a signal indicating OV7670 module has come to the requested point,
-- launch the pump out function - pump data from WorkGD to a stream
when others =>
end case;
else
stateFSM1 <= s1;
end if;
end if;
end process FSM1;
I'm working on digital clock using VHDL Altera board. And I've got stuck during coding. I was trying to make a digital clock that shows hours, minutes, and seconds on six 7-segments. My code is like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_main is
port(clk_50mhz, reset, min_sw, hour_sw: in std_logic;
fnd_s: out std_logic_vector(5 downto 0);
fnd_d: out std_logic_vector(7 downto 0));
end time_main;
architecture clock of time_main is
signal clk_cnt: integer range 0 to 50000000;
signal data1, data3, data5, temp: integer range 0 to 9;
signal data2, data4: integer range 0 to 5;
signal data6: integer range 0 to 2;
signal cnt: integer range 0 to 5;
signal clk_test: integer range 0 to 5000000000;
variable decode_seg: std_logic_vector(7 downto 0);
begin
case count_seg is
when 0 => decode_seg := "00111111";
when 1 => decode_seg := "00000110";
when 2 => decode_seg := "01011011";
when 3 => decode_seg := "01001111";
when 4 => decode_seg := "01100110";
when 5 => decode_seg := "01101101";
when 6 => decode_seg := "01111101";
when 7 => decode_seg := "00100111";
when 8 => decode_seg := "01111111";
when 9 => decode_seg := "01101111";
when others => decode_seg := "00000000";
end case;
return(decode_seg);
end dis_7_seg;
begin
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
sec_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data1 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
data1 <= 0;
else
data1 <= data1 + 1;
end if;
end if;
end if;
end process;
sec_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data2 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
if(data2 = 5) then
data2 <= 0;
else
data2 <= data2 + 1;
end if;
end if;
end if;
end if;
end process;
min_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data3 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
end if;
end if;
end process;
min_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data4 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
if(clk_cnt = 50000000) then
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
end if;
end if;
end process;
hour_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data5 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9) then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9)then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
end if;
end if;
end process;
hour_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data6 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then -
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_test = 5000000000) then
clk_test <= 0;
else
clk_test <= clk_test + 1;
end if;
end if;
end process;
process(clk_test)
begin
if(clk_test = 5000000000) then
if(cnt = 5) then
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process;
process(data1, data2, data3, data4, data5, data6, cnt)
begin
If (cnt=0) then
fnd_s <= "000001";
temp <= data1;
else if(cnt=1) then
fnd_s <= "000010";
temp <= data2;
else if (cnt=2) then
fnd_s <= "000100";
temp <= data3;
else if (cnt=3) then
fnd_s <= "001000";
temp <= data4;
else if (cnt=4) then
fnd_s <= "010000";
temp <= data5;
else if (cnt=5) then
fnd_s <= "100000";
temp <= data6;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
fnd_d <= dis_7_seg(temp);
end clock;
========================================================================
however, the i found out that the first segment did not show anything, just total OFF... and I found that other 5 segments show the same number: from 0 to 9 for 9 seconds, and then the segments show 0 again and keep counting from 0 to 9. I thought I made a good code enough to make hours, minutes, and seconds... but it shows only seconds.... Can anyone tell me what's wrong with my code.. please?
I am working on my college project a digital clock on altera board. the problem i am facing is my hours goes to 29 instead of 24! I am using integer type for my hours right digit ranging 0 to 9; i got if statement that when my hours left digit is 2 and hours right digit is 3 i want my second, minutes and hours 00:00:00.. But its not implementing why? Need some advice... Thanks
here is my code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity master is
port(
clk : in std_logic;
hrs_lft : out std_logic_vector(1 downto 0 );
hrs_rght : out std_logic_vector(3 downto 0 );
min_lft : out std_logic_vector(2 downto 0 );
min_rght : out std_logic_vector(3 downto 0 );
second_lft: out std_logic_vector(2 downto 0);
second_rght : out std_logic_vector( 3 downto 0)
);
end master;
architecture bhv of master is
signal second_lft_int : integer range 0 to 5;
signal second_rght_int : integer range 0 to 9;
signal min_lft_int : integer range 0 to 5;
signal min_rght_int : integer range 0 to 9;
signal hrs_lft_int : integer range 0 to 2;
signal hrs_rght_int : integer range 0 to 9;
begin
process(clk)
begin
if (rising_edge(clk)) then
second_rght_int <= second_rght_int + 1;
if second_rght_int = 9 then
second_lft_int <= second_lft_int + 1;
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
min_rght_int <= min_rght_int + 1;
if min_rght_int = 9 then
min_lft_int <= min_lft_int + 1;
min_rght_int <= 0;
if min_rght_int = 5 then
hrs_rght_int <= hrs_rght_int + 1;
min_rght_int <= 0;
if hrs_rght_int = 9 then
hrs_lft_int <= hrs_lft_int + 1;
if (hrs_rght_int = 3 and hrs_lft_int = 2) then
hrs_lft_int <= 0;
hrs_rght_int <= 0;
min_lft_int <= 0;
min_rght_int <= 0;
second_rght_int <= 0;
second_lft_int <= 0;
end if ;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
second_rght<= std_logic_vector(to_unsigned(second_rght_int,second_rght'length));
second_lft<=std_logic_vector(to_unsigned(second_lft_int,second_lft'length));
min_rght<= std_logic_vector(to_unsigned(min_rght_int,min_rght 'length));
min_lft <= std_logic_vector(to_unsigned(min_lft_int,min_lft'length));
hrs_rght<= std_logic_vector(to_unsigned(hrs_rght_int,hrs_rght 'length));
hrs_lft <= std_logic_vector(to_unsigned(hrs_lft_int,hrs_lft'length));
end bhv;
You process didn't look right, so I wrote it de novo:
process (clk)
begin
if rising_edge(clk) then
if second_rght_int = 9 then
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
if min_rght_int = 9 then
min_rght_int <= 0;
if min_lft_int = 5 then
min_lft_int <= 0;
if (hrs_lft_int = 2 and hrs_rght_int = 4)
or hrs_rght_int = 9 then
hrs_rght_int <= 0;
if hrs_lft_int = 2 then
hrs_lft_int <= 0;
else
hrs_lft_int <= hrs_lft_int + 1;
end if;
else
hrs_rght_int <= hrs_rght_int + 1;
end if;
else
min_lft_int <= min_lft_int + 1;
end if;
else
min_rght_int <= min_rght_int + 1;
end if;
else
second_lft_int <= second_lft_int + 1;
end if;
else
second_rght_int <= second_rght_int + 1;
end if;
end if;
end process;
And that gives:
In VHDL "+" for integer is defined as an operation on a type integer and not a modular integer, you have to check for the boundary condition yourself.
You might also notice I set the clk rate to 1 ps in simulation. A bit excessive but I wanted to search for roll over events.
A testbench can consist of as little as a direct entity instantiation with a single port association for the clk. (The waveforms are from the Device Under Test).
I've got a problem with a synthesis of that code.
The error which is shown is "Signal blk_pointer cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.".
I want to save communication messages between two devices. The part with falling_edge and rising_edge is to find a current part of message, and create a pointer to that part (msg_pointer, blk_pointer). Then I want to save the current value to a buffer.
It works when I delete the last part ( that with for loop).
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable buf_pointer : INTEGER range 0 to 13:=0; --pointing to a number of bit in the output S14T7C7_TEMP buf
variable S14T7C7_TEMP : STD_LOGIC_VECTOR (13 downto 0):="00000000000000";
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if falling_edge(com_delayed) then
if com_level_time > 4500 then
msg_pointer := 0;
blk_pointer := 0;
buf_pointer := 0;
elsif ( com_level_time < 4500 ) and ( com_level_time > 630 ) then
msg_pointer := 1;
blk_pointer := 0;
buf_pointer := 0;
elsif blk_pointer >= 9 then
blk_pointer:=0;
if msg_pointer<6 then
msg_pointer:=msg_pointer+1;
end if;
elsif com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
njed:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
njed:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
njed:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
njed:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
njed:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
njed:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
njed:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
njed:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
njed:=9;
copy:='1';
end if;
end if;
if rising_edge(com_delayed) then
if com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
nzer:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
nzer:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
nzer:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
nzer:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
nzer:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
nzer:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
nzer:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
nzer:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
nzer:=9;
copy:='1';
end if;
end if;
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
if copy='1' then
For it in 1 to 9 loop
if nzer/=0 then
message1(msg_pointer_ext)(blk_pointer_ext-nzer):='0';
nzer:=nzer-1;
end if;
end loop;
end if;
copy:='0';
end process;
New two processes:
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if rising_edge(com_delayed) then
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
nzer:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
nzer:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
nzer:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
nzer:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
nzer:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
nzer:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
nzer:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
nzer:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
nzer:=9;
copy:='1';
end if;
if copy='1' then
For it in 1 to 9 loop
if nzer/=0 then
message1(msg_pointer)(blk_pointer-nzer):='0';
nzer:=nzer-1;
end if;
end loop;
end if;
copy:='0';
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
end process;
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if falling_edge(com_delayed) then
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if com_level_time > 4500 then
msg_pointer := 0;
blk_pointer := 0;
elsif ( com_level_time < 4500 ) and ( com_level_time > 630 ) then
msg_pointer := 1;
blk_pointer := 0;
elsif blk_pointer >= 9 then
blk_pointer:=0;
if msg_pointer<6 then
msg_pointer:=msg_pointer+1;
end if;
elsif com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
njed:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
njed:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
njed:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
njed:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
njed:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
njed:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
njed:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
njed:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
njed:=9;
copy:='1';
end if;
if copy='1' then
For it in 1 to 9 loop
if njed/=0 then
message1(msg_pointer)(blk_pointer-njed):='0';
njed:=njed-1;
end if;
end loop;
end if;
copy:='0';
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
end process;
Next error is : Multi-Source on Integers in concurrent assignment. (external pointers)
And new version without errors:
process(clk_com, com_ecu38)
variable com_clear : STD_LOGIC:='0';
variable tclt : INTEGER range 0 to 32000:=0;
begin
if rising_edge(clk_com) and tclt /= 31999 then
tclt := tclt +1;
end if;
if com_ecu38'event then
com_level_time:=tclt;
com_clear:='1';
end if;
if com_clear='1' then
tclt:=0;
com_delayed<=com_ecu38;
end if;
com_clear:='0';
end process;
process(com_delayed)
begin
if rising_edge(com_delayed) then
if com_level_time>20 and com_level_time<=80 then
nzer:=1;
elsif (com_level_time>80 and com_level_time<=142) then
nzer:=2;
elsif (com_level_time>142 and com_level_time<=200) then
nzer:=3;
elsif (com_level_time>200 and com_level_time<=274) then
nzer:=4;
elsif (com_level_time>274 and com_level_time<=336) then
nzer:=5;
elsif (com_level_time>336 and com_level_time<=396) then
nzer:=6;
elsif (com_level_time>396 and com_level_time<=460) then
nzer:=7;
elsif (com_level_time>460 and com_level_time<=526) then
nzer:=8;
elsif (com_level_time>526 and com_level_time<=630) then
nzer:=9;
else
nzer:=0;
end if;
copy0<=not(copy0);
end if;
end process;
process(com_delayed)
begin
if falling_edge(com_delayed) then
if com_level_time > 4500 then
njed:=12;
elsif com_level_time > 630 and com_level_time <= 4500 then
njed:=11;
elsif com_level_time>20 and com_level_time<=80 then
njed:=1;
elsif (com_level_time>80 and com_level_time<=142) then
njed:=2;
elsif (com_level_time>142 and com_level_time<=200) then
njed:=3;
elsif (com_level_time>200 and com_level_time<=274) then
njed:=4;
elsif (com_level_time>274 and com_level_time<=336) then
njed:=5;
elsif (com_level_time>336 and com_level_time<=396) then
njed:=6;
elsif (com_level_time>396 and com_level_time<=460) then
njed:=7;
elsif (com_level_time>460 and com_level_time<=526) then
njed:=8;
elsif (com_level_time>526 and com_level_time<=630) then
njed:=9;
else
njed:=0;
end if;
copy1<=not(copy1);
end if;
end process;
process(copy1, copy0)
variable n : INTEGER range 0 to 9:=0;
variable bit_to_write : STD_LOGIC;
variable inc_msg : STD_LOGIC;
variable c1 : STD_LOGIC;
variable c0 : STD_LOGIC;
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
begin
if copy1'event then
n:=njed;
c1:='1';
elsif copy0'event then
n:=nzer;
c0:='1';
end if;
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if c1='1' then
bit_to_write:='1';
elsif c0='1' then
bit_to_write:='0';
end if;
if n=12 then
msg_pointer:=0;
blk_pointer:=0;
com_ch_out<=not(com_ch_out);
elsif n=11 then
msg_pointer:=1;
blk_pointer:=0;
else
if blk_pointer + n <9 then
blk_pointer:=blk_pointer+n;
else
n:=9-blk_pointer;
inc_msg:='1';
blk_pointer:=9;
end if;
For it in 1 to 9 loop
if n/=0 then
message1(msg_pointer)(blk_pointer-n):=bit_to_write;
n:=n-1;
end if;
end loop;
end if;
if inc_msg='1' then
if msg_pointer<5 then
blk_pointer_ext:=0;
msg_pointer_ext:=msg_pointer+1;
end if;
else
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
n:=0;
inc_msg:='0';
c1:='0';
c0:='0';
end process;
process(com_ch_out)
begin
if com_ch_out'event then
if latch_outputs='0' then
if stc_decide = '0' then
S14T7C7(0)<=message1(1)(1);
S14T7C7(1)<=message1(1)(2);
S14T7C7(2)<=message1(1)(3);
S14T7C7(3)<=message1(1)(4);
S14T7C7(4)<=message1(1)(5);
S14T7C7(5)<=message1(1)(6);
S14T7C7(6)<=message1(1)(7);
S14T7C7(7)<=message1(2)(1);
S14T7C7(8)<=message1(2)(2);
S14T7C7(9)<=message1(2)(3);
S14T7C7(10)<=message1(2)(4);
S14T7C7(11)<=message1(2)(5);
S14T7C7(12)<=message1(2)(6);
S14T7C7(13)<=message1(2)(7);
else
S14T7C7(0)<=message1(4)(1);
S14T7C7(1)<=message1(4)(2);
S14T7C7(2)<=message1(4)(3);
S14T7C7(3)<=message1(4)(4);
S14T7C7(4)<=message1(4)(5);
S14T7C7(5)<=message1(4)(6);
S14T7C7(6)<=message1(4)(7);
S14T7C7(7)<=C7I(0);
S14T7C7(8)<=C7I(1);
S14T7C7(9)<=C7I(2);
S14T7C7(10)<=C7I(3);
S14T7C7(11)<=C7I(4);
S14T7C7(12)<=C7I(5);
S14T7C7(13)<=C7I(6);
end if;
end if;
end if;
end process;
strong text
Whenver I try to synthesize my code, it is caught in an infinite loop i.e it is stuck at HDL SYNTHESIS. I have not used any loops. But problem persists.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mat is
port(
start,clck,start4,add4,check4,delete3,start3,add3,final3,load,load3,load4,search3:in std_logic;
data1,data2,newitem:in std_logic_vector(0 to 8);
completeload4tocontroller,completeadd3,search3cmplt,completeload3tocontroller,
completeloadtocontroller,discerncomplete,complete4add,completedel3,step4comptocntrl:out bit;
data4,data6:out std_logic_vector(0 to 15));
end mat;
architecture Behavioral of mat is
type positiveelem is array (0 to 255) of std_logic_vector(0 to 18);
type negativeelem is array (0 to 255) of std_logic_vector(0 to 18);
signal poselem:positiveelem ;
signal negelem:negativeelem ;
signal pospointer:integer range 0 to 255:=0;
signal negpointer:integer range 0 to 255:=0;
signal jpst:integer range 0 to 255 := 0;
signal jnst:integer range 0 to 255 := 0;
signal jp1st:integer range 0 to 255 := 0;
signal jp2st:integer range 0 to 255 := 0;
signal jn4st:integer range 0 to 255 := 0;
signal jp4st:integer range 0 to 255 := 0;
signal j3pntr:integer range 0 to 255 := 0;
signal j3npntr:integer range 0 to 255 := 0;
signal j3ptr:integer range 0 to 255 := 0;
type list12 is array(0 to 65535) of integer range 0 to 31;
signal clist:list12;
signal limitcount:integer range 0 to 255 :=0;
signal flag1:std_logic :='0';
signal position:integer range 0 to 255;
begin
P1:process(load,load4,clck,load3,check4,start,add4,start4,start3,delete3,add3)
variable temp4:std_logic_vector(0 to 15);
variable temp5:std_logic_vector(0 to 15);
variable temp1:std_logic_vector(0 to 15);
variable tempp3:std_logic_vector(0 to 15);
begin
if(rising_edge(clck))then
if(load='1')then
poselem(pospointer) <= data1;
negelem(negpointer) <= data2;
pospointer <= pospointer + 1;
negpointer <= negpointer + 1;
limitcount <= limitcount + 1;
if(limitcount = 10)then
completeloadtocontroller <= '1';
end if;
elsif((load4 = '1') and (load ='0'))then
poselem(pospointer) <= newitem;
pospointer <= pospointer + 1;
completeload4tocontroller <= '1';
elsif((load3 = '1') and (load = '0'))then
negelem(negpointer) <= newitem;
negpointer <= negpointer + 1;
completeload3tocontroller <= '1';
elsif(start = '1')then
if((jpst <= pospointer) and (jnst <= negpointer))then
temp4 := poselem(jpst)(0 to 15) xor negelem(jnst)(0 to 15);
clist(conv_integer(temp4)) <= clist(conv_integer(temp4)) + 1;
if((jnst = (negpointer - 1)) and (jpst < (pospointer - 1)))then
jnst <= 0;
jpst <= jpst + 1;
elsif(jnst < (negpointer - 1) and (jpst < (pospointer - 1)))then
jnst <= jnst + 1;
elsif(jpst = (pospointer - 1) and (jnst < (negpointer - 1)))then
jnst <= jnst + 1;
elsif((jp1st = pospointer) and (jp2st = pospointer) and
(jpst = pospointer) and (jnst = negpointer))then
discerncomplete <= '1';
end if;
end if;
elsif(start4 = '1')then
if(add4 = '1')then
temp1 := newitem(0 to 15) xor negelem(jn4st)(0 to 15);
if(clist(conv_integer(temp1)) = 0)then
data4 <= temp1;
end if;
clist(conv_integer(temp1)) <= clist(conv_integer(temp1)) + 1;
if(jn4st < (negpointer - 1))then
jn4st <= jn4st + 1;
elsif((jp4st = pospointer - 1) and (jn4st = negpointer - 1))then
complete4add <= '1';
end if;
end if;
elsif(start3 = '1')then
if(delete3 = '1')then
if((poselem(position)(0 to 15) /= poselem(j3pntr))
and (poselem(position)(16 to 18) /= poselem(j3pntr)(16 to 18)))then
tempp3 := poselem(position)(0 to 15) xor poselem(j3pntr)(0 to 15);
if(clist(conv_integer(tempp3)) = 1)then
data6 <= tempp3;
end if;
if(clist(conv_integer(tempp3)) /= 0)then
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) - 1;
end if;
if(j3pntr < (pospointer - 1))then
j3pntr <= j3pntr + 1;
elsif((j3pntr = pospointer - 1) and (j3npntr = negpointer - 1))then
completedel3 <= '1';
poselem(position) <= "0000000000000000000";
end if;
end if;
elsif(search3 = '1')then
if((poselem(position)(16 to 18) /= newitem(16 to 18))
and (poselem(position)(0 to 15) = newitem(0 to 15)))then
flag1 <= '1';
end if;
if((position < pospointer) and (flag1 = '0'))then
position <= position + 1;
elsif(flag1 = '1')then
search3cmplt <= '1';
end if;
elsif(add3 = '1')then
tempp3 := newitem(0 to 15) xor poselem(j3ptr)(0 to 15);
if(clist(conv_integer(tempp3)) = 0)then
data4 <= tempp3;
end if;
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) + 1;
if(j3ptr < pospointer - 1 and (j3ptr = (position - 1)))then
j3ptr <= j3ptr + 2;
elsif(j3ptr = (pospointer - 1))then
completeadd3 <= '1';
else
j3ptr <= j3ptr + 1;
end if;
end if;
end if;
end if;
if(falling_edge(clck))then
if(start = '1')then
if((jp1st /= pospointer) and (jp2st /= pospointer) and (poselem(jp1st)(16 to 18) /= poselem(jp2st)(16 to 18))
and (poselem(jp1st)(0 to 15) /= poselem(jp2st)(0 to 15))) then
temp5 := poselem(jp1st)(0 to 15) xor poselem(jp2st)(0 to 15);
clist(conv_integer(temp5)) <= clist(conv_integer(temp5)) + 1;
end if;
if(jp1st < (pospointer - 1) and jp2st = (pospointer-1))then
jp1st <= jp1st + 1;
jp2st <= 0;
elsif(jp1st = (pospointer - 1) and jp2st < (pospointer-1))then
jp2st <= jp2st + 1;
elsif(jp1st < (pospointer - 1) and jp2st < (pospointer-1))then
jp2st <= jp2st + 1;
elsif((jp1st = pospointer) and (jp2st = pospointer) and (jpst = pospointer) and (jnst = negpointer))then
discerncomplete <= '1';
end if;
elsif(start4 = '1')then
if(add4 = '1')then
if((poselem(jp4st)(0 to 15) /= "0000000000000000"))then
if(poselem(jp4st)(0 to 15) /= newitem(0 to 15))
and (poselem(jp4st)(16 to 18) /= newitem(16 to 18)))then
temp1 := newitem(0 to 15) xor poselem(jp4st)(0 to 15);
if(clist(conv_integer(temp1)) = 0)then
data4 <= temp1;
end if;
clist(conv_integer(temp1)) <= clist(conv_integer(temp1)) + 1;
end if;
if(jp4st < (pospointer - 1))then
jp4st <= jp4st + 1;
elsif((jp4st = pospointer - 1) and (jn4st = negpointer - 1))then
complete4add <= '1';
end if;
end if;
elsif(start3 = '1')then
if(delete3 = '1')then
tempp3 := newitem(0 to 15) xor negelem(j3npntr)(0 to 15);
if(clist(conv_integer(tempp3)) = 1)then
data6 <= tempp3;
end if;
if(clist(conv_integer(tempp3)) = 0)then
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) - 1;
end if;
if(j3npntr < negpointer - 1 )then
j3npntr <= j3npntr + 1;
elsif((j3pntr = pospointer - 1) and (j3npntr = negpointer - 1))then
completedel3 <= '1';
poselem(position) <= "0000000000000000000";
end if;
end if;
end if;
end if;
end process P1;
end Behavioral;
My comments address some of these issues, but I thought I'd type them up as an answer to add a little more detail and clarification.
Synthesis software getting stuck at a certain step and locking up has little to nothing to do with any particular language structure you're using, and probably means the software is having trouble parsing your code. While I would call this a bug in the software, you can probably get around it by looking for syntax errors (using another compiler, like ModelSim or something, might also help, if you have access). For instance, you appear to have an if-loop you're not closing somewhere under if falling_edge(clck). You also have a missing ( on the lines:
if(poselem(jp4st)(0 to 15) /= newitem(0 to 15))
and (poselem(jp4st)(16 to 18) /= newitem(16 to 18)))then
And you're assigning data1, a 9-bit vector, to poselem(pospointer), a 19-bit vector (and other similar assignments). Check your port and signal definitions.