Need advice for my vhdl code - vhdl

Question

I am working on my college project a digital clock on altera board. the problem i am facing is my hours goes to 29 instead of 24! I am using integer type for my hours right digit ranging 0 to 9; i got if statement that when my hours left digit is 2 and hours right digit is 3 i want my second, minutes and hours 00:00:00.. But its not implementing why? Need some advice... Thanks
here is my code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity master is
port(
clk : in std_logic;
hrs_lft : out std_logic_vector(1 downto 0 );
hrs_rght : out std_logic_vector(3 downto 0 );
min_lft : out std_logic_vector(2 downto 0 );
min_rght : out std_logic_vector(3 downto 0 );
second_lft: out std_logic_vector(2 downto 0);
second_rght : out std_logic_vector( 3 downto 0)
);
end master;
architecture bhv of master is
signal second_lft_int : integer range 0 to 5;
signal second_rght_int : integer range 0 to 9;
signal min_lft_int : integer range 0 to 5;
signal min_rght_int : integer range 0 to 9;
signal hrs_lft_int : integer range 0 to 2;
signal hrs_rght_int : integer range 0 to 9;
begin
process(clk)
begin
if (rising_edge(clk)) then
second_rght_int <= second_rght_int + 1;
if second_rght_int = 9 then
second_lft_int <= second_lft_int + 1;
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
min_rght_int <= min_rght_int + 1;
if min_rght_int = 9 then
min_lft_int <= min_lft_int + 1;
min_rght_int <= 0;
if min_rght_int = 5 then
hrs_rght_int <= hrs_rght_int + 1;
min_rght_int <= 0;
if hrs_rght_int = 9 then
hrs_lft_int <= hrs_lft_int + 1;
if (hrs_rght_int = 3 and hrs_lft_int = 2) then
hrs_lft_int <= 0;
hrs_rght_int <= 0;
min_lft_int <= 0;
min_rght_int <= 0;
second_rght_int <= 0;
second_lft_int <= 0;
end if ;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
second_rght<= std_logic_vector(to_unsigned(second_rght_int,second_rght'length));
second_lft<=std_logic_vector(to_unsigned(second_lft_int,second_lft'length));
min_rght<= std_logic_vector(to_unsigned(min_rght_int,min_rght 'length));
min_lft <= std_logic_vector(to_unsigned(min_lft_int,min_lft'length));
hrs_rght<= std_logic_vector(to_unsigned(hrs_rght_int,hrs_rght 'length));
hrs_lft <= std_logic_vector(to_unsigned(hrs_lft_int,hrs_lft'length));
end bhv;

Answer 1

You process didn't look right, so I wrote it de novo:
process (clk)
begin
if rising_edge(clk) then
if second_rght_int = 9 then
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
if min_rght_int = 9 then
min_rght_int <= 0;
if min_lft_int = 5 then
min_lft_int <= 0;
if (hrs_lft_int = 2 and hrs_rght_int = 4)
or hrs_rght_int = 9 then
hrs_rght_int <= 0;
if hrs_lft_int = 2 then
hrs_lft_int <= 0;
else
hrs_lft_int <= hrs_lft_int + 1;
end if;
else
hrs_rght_int <= hrs_rght_int + 1;
end if;
else
min_lft_int <= min_lft_int + 1;
end if;
else
min_rght_int <= min_rght_int + 1;
end if;
else
second_lft_int <= second_lft_int + 1;
end if;
else
second_rght_int <= second_rght_int + 1;
end if;
end if;
end process;
And that gives:
In VHDL "+" for integer is defined as an operation on a type integer and not a modular integer, you have to check for the boundary condition yourself.
You might also notice I set the clk rate to 1 ps in simulation. A bit excessive but I wanted to search for roll over events.
A testbench can consist of as little as a direct entity instantiation with a single port association for the clk. (The waveforms are from the Device Under Test).