I'm working on digital clock using VHDL Altera board. And I've got stuck during coding. I was trying to make a digital clock that shows hours, minutes, and seconds on six 7-segments. My code is like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_main is
port(clk_50mhz, reset, min_sw, hour_sw: in std_logic;
fnd_s: out std_logic_vector(5 downto 0);
fnd_d: out std_logic_vector(7 downto 0));
end time_main;
architecture clock of time_main is
signal clk_cnt: integer range 0 to 50000000;
signal data1, data3, data5, temp: integer range 0 to 9;
signal data2, data4: integer range 0 to 5;
signal data6: integer range 0 to 2;
signal cnt: integer range 0 to 5;
signal clk_test: integer range 0 to 5000000000;
variable decode_seg: std_logic_vector(7 downto 0);
begin
case count_seg is
when 0 => decode_seg := "00111111";
when 1 => decode_seg := "00000110";
when 2 => decode_seg := "01011011";
when 3 => decode_seg := "01001111";
when 4 => decode_seg := "01100110";
when 5 => decode_seg := "01101101";
when 6 => decode_seg := "01111101";
when 7 => decode_seg := "00100111";
when 8 => decode_seg := "01111111";
when 9 => decode_seg := "01101111";
when others => decode_seg := "00000000";
end case;
return(decode_seg);
end dis_7_seg;
begin
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
sec_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data1 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
data1 <= 0;
else
data1 <= data1 + 1;
end if;
end if;
end if;
end process;
sec_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data2 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
if(data2 = 5) then
data2 <= 0;
else
data2 <= data2 + 1;
end if;
end if;
end if;
end if;
end process;
min_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data3 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
end if;
end if;
end process;
min_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data4 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
if(clk_cnt = 50000000) then
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
end if;
end if;
end process;
hour_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data5 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9) then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9)then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
end if;
end if;
end process;
hour_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data6 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then -
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_test = 5000000000) then
clk_test <= 0;
else
clk_test <= clk_test + 1;
end if;
end if;
end process;
process(clk_test)
begin
if(clk_test = 5000000000) then
if(cnt = 5) then
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process;
process(data1, data2, data3, data4, data5, data6, cnt)
begin
If (cnt=0) then
fnd_s <= "000001";
temp <= data1;
else if(cnt=1) then
fnd_s <= "000010";
temp <= data2;
else if (cnt=2) then
fnd_s <= "000100";
temp <= data3;
else if (cnt=3) then
fnd_s <= "001000";
temp <= data4;
else if (cnt=4) then
fnd_s <= "010000";
temp <= data5;
else if (cnt=5) then
fnd_s <= "100000";
temp <= data6;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
fnd_d <= dis_7_seg(temp);
end clock;
========================================================================
however, the i found out that the first segment did not show anything, just total OFF... and I found that other 5 segments show the same number: from 0 to 9 for 9 seconds, and then the segments show 0 again and keep counting from 0 to 9. I thought I made a good code enough to make hours, minutes, and seconds... but it shows only seconds.... Can anyone tell me what's wrong with my code.. please?
Related
i'm working on a project using vhdl to configure a fpga board spartan 3E. what i have to do is a genius puzzle, in my main code there is a state machine to control the logic.
everything works well when i simulate the code using xilinx simulator but when i run the .bit file to the FPGA board what happens is that the first led of the sequence turns on and then turns off, this should happen but then when i click the right button it just stop working and the next sequence is never shown.
of course there is a issue of deboucing the buttons, and that's the reason i'm using a counter to prevent the repic to bug the system.
i'm working hard on this code to function but this issue doesn't go away, maybe i'm doing something wrong i don't know or i'm not doing something i should.
here is my main code, which is the state machine and a clock proccess with the counter.
Flag_conte = starts ou blocks the counter
Flag_estou_contando = 1=counting, 0= not counting, 3= just finished count.
BCD = board buttons IN
LEDs = corresponds to 4 leds that will show the sequence in the game
entity Algoritmo is
port(
clk: in std_logic;
BCD: in std_logic_vector (3 downto 0);
botaoStart: in std_logic;
botaoReset: in std_logic;
seven_seg: out std_logic_vector(6 downto 0);
anode: out std_logic_vector(3 downto 0);
LEDS: out std_logic_vector(3 downto 0)
);
END Algoritmo;
architecture Behavioral of Algoritmo is
subtype state_type is integer range 5 downto 0;
signal state, nextstate: state_type:=0;
signal Inicio, nclk: std_logic:= '0';
--variable posicaoAtual: integer :=0;
type mem1 is array (0 to 13) of std_logic_vector (3 downto 0);
constant vetorSequencia: mem1 := ( "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010");
constant generic1hz: integer:= 12_500_000;
signal t3count:integer:=0;
signal posA, posB, signalScore, Flag_conte,
Flag_estou_contando:integer:=0;
signal valor: integer :=12_500_000;
Begin
-------------
process (state,BCD,botaoStart,Flag_estou_contando)
variable Pos: integer :=0;
variable score: integer:=0;
variable posicaoAtual: integer:=0;
variable tentativa: std_logic_vector (3 downto 0);
begin
case state is
when 0 => if (botaoStart = '0')
then nextstate <= 0;-- estado idle, esperando entrada do tclado,led1=1;
else nextstate <= 1;
end if;
when 1 =>-- if(Flag_estou_contando =0)then
if(nextstate=2)then
Flag_conte <=0;
nextstate <= 2;
else if (nextstate/=2)then
if (posicaoAtual < score)then
if(Flag_estou_contando=0)then
LEDS <= vetorSequencia(posicaoAtual);
posA <= posicaoAtual;
Flag_conte<=1;
valor<=10_000_000;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
else if (Flag_estou_contando=3)then
--posicaoAtual:=0;
posicaoAtual := posicaoAtual + 1;
posA <= posicaoAtual;
nextstate <=1;
Flag_conte<=0;
end if;end if;end if;
else if(posicaoAtual = score)then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=10_000_000;
-- posicaoAtual :=0;
posA <= posicaoAtual;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
nextstate<=1;
else if(Flag_estou_contando=3)then
posicaoAtual:=0;
posA <= posicaoAtual;
Flag_conte<=0;
nextstate <= 2;
end if;end if;end if;
end if;end if;
Flag_conte <=1;
end if;end if;
when 2 => --if(Flag_estou_contando=0)then
if (BCD = "0000")then
if(Flag_estou_contando=0)then
LEDS <= "0000"; --nextstate <= 2;
else if (Flag_estou_contando=1)then
nextstate<=2;
else if (Flag_estou_contando=3)then
Flag_conte <= 0;
nextstate<=3;
end if;end if;end if;
else if(BCD /= "0000")then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=200_000_000;
tentativa := BCD;
LEDS <= tentativa;
else if(Flag_estou_contando=3)then
nextstate <= 3;
else if(Flag_estou_contando=1)then
LEDS <= tentativa;
nextstate <=2;
end if;end if;end if;
end if;end if;
when 3 => if (vetorSequencia(Pos) = tentativa)then
if (Pos < score)then
nextstate <= 2;
Pos := Pos + 1;
posB <= Pos;
else if(Pos = score)then
score := score + 1;
signalScore <= score;
nextstate <= 1;
Pos := 0;
if (score = 15)-- if score =15 finish game
then nextstate <= 5;
end if;--end if
end if;end if;
else -- se estiver errado, perde o jogo
nextstate <= 4; -- goes to game over
end if;
when 4 => if (botaoReset = '1') -- game over
then nextstate <= 4;-- "U LOST nOOB"
elsif (botaoReset = '0')
then nextstate <= 0; --
end if;
when 5 => if (botaoReset = '1') -- jogo ganho
then nextstate <= 5; -- "GG"
elsif (botaoReset = '0')
then nextstate <= 0;
end if;
end case;
end process;
process (clk, Flag_conte)
variable sum, count :integer:=0;
begin
if rising_edge(clk) then
if(Flag_estou_contando = 0) then
if (Flag_conte = 1) then
count :=0;
Flag_estou_contando <=1;
end if;
end if;
if(Flag_estou_contando=3) then
if(Flag_conte =0)then
Flag_estou_contando <= 0;
else
Flag_estou_contando <=3;
end if;
end if;
if (Flag_estou_contando =1)then
if(count < valor)then
count := count + 1;
else
count:=0;
Flag_estou_contando <=3;
end if;
end if;
sum := sum +1;
if(sum = generic1hz)then -- 1hz generate
state <= nextstate;
nclk <= not nclk;
sum := 0;--restart count for 1hz generate
end if;
end if;
end process;
end Behavioral;
if i wasnt clear, please let me know i will try to explain better, if anyone could help i would be very greatful, thank you for your time.
You should try post place & route simulation to verify whats happen:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_simulate_post_place.htm
With some family device you can use chipscope technology to debug:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm
Sorry for my English.
Regards.
I am working on my college project a digital clock on altera board. the problem i am facing is my hours goes to 29 instead of 24! I am using integer type for my hours right digit ranging 0 to 9; i got if statement that when my hours left digit is 2 and hours right digit is 3 i want my second, minutes and hours 00:00:00.. But its not implementing why? Need some advice... Thanks
here is my code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity master is
port(
clk : in std_logic;
hrs_lft : out std_logic_vector(1 downto 0 );
hrs_rght : out std_logic_vector(3 downto 0 );
min_lft : out std_logic_vector(2 downto 0 );
min_rght : out std_logic_vector(3 downto 0 );
second_lft: out std_logic_vector(2 downto 0);
second_rght : out std_logic_vector( 3 downto 0)
);
end master;
architecture bhv of master is
signal second_lft_int : integer range 0 to 5;
signal second_rght_int : integer range 0 to 9;
signal min_lft_int : integer range 0 to 5;
signal min_rght_int : integer range 0 to 9;
signal hrs_lft_int : integer range 0 to 2;
signal hrs_rght_int : integer range 0 to 9;
begin
process(clk)
begin
if (rising_edge(clk)) then
second_rght_int <= second_rght_int + 1;
if second_rght_int = 9 then
second_lft_int <= second_lft_int + 1;
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
min_rght_int <= min_rght_int + 1;
if min_rght_int = 9 then
min_lft_int <= min_lft_int + 1;
min_rght_int <= 0;
if min_rght_int = 5 then
hrs_rght_int <= hrs_rght_int + 1;
min_rght_int <= 0;
if hrs_rght_int = 9 then
hrs_lft_int <= hrs_lft_int + 1;
if (hrs_rght_int = 3 and hrs_lft_int = 2) then
hrs_lft_int <= 0;
hrs_rght_int <= 0;
min_lft_int <= 0;
min_rght_int <= 0;
second_rght_int <= 0;
second_lft_int <= 0;
end if ;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
second_rght<= std_logic_vector(to_unsigned(second_rght_int,second_rght'length));
second_lft<=std_logic_vector(to_unsigned(second_lft_int,second_lft'length));
min_rght<= std_logic_vector(to_unsigned(min_rght_int,min_rght 'length));
min_lft <= std_logic_vector(to_unsigned(min_lft_int,min_lft'length));
hrs_rght<= std_logic_vector(to_unsigned(hrs_rght_int,hrs_rght 'length));
hrs_lft <= std_logic_vector(to_unsigned(hrs_lft_int,hrs_lft'length));
end bhv;
You process didn't look right, so I wrote it de novo:
process (clk)
begin
if rising_edge(clk) then
if second_rght_int = 9 then
second_rght_int <= 0;
if second_lft_int = 5 then
second_lft_int <= 0;
if min_rght_int = 9 then
min_rght_int <= 0;
if min_lft_int = 5 then
min_lft_int <= 0;
if (hrs_lft_int = 2 and hrs_rght_int = 4)
or hrs_rght_int = 9 then
hrs_rght_int <= 0;
if hrs_lft_int = 2 then
hrs_lft_int <= 0;
else
hrs_lft_int <= hrs_lft_int + 1;
end if;
else
hrs_rght_int <= hrs_rght_int + 1;
end if;
else
min_lft_int <= min_lft_int + 1;
end if;
else
min_rght_int <= min_rght_int + 1;
end if;
else
second_lft_int <= second_lft_int + 1;
end if;
else
second_rght_int <= second_rght_int + 1;
end if;
end if;
end process;
And that gives:
In VHDL "+" for integer is defined as an operation on a type integer and not a modular integer, you have to check for the boundary condition yourself.
You might also notice I set the clk rate to 1 ps in simulation. A bit excessive but I wanted to search for roll over events.
A testbench can consist of as little as a direct entity instantiation with a single port association for the clk. (The waveforms are from the Device Under Test).
My code is about a ping pang game using VHDL and maxplus2. I can't get it complied.
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;
entity center is
port (
clk: in std_logic;
ca: in std_logic;
cb: in std_logic;
enable: in std_logic;
a: in std_logic;
b: in std_logic;
ball: out std_logic_vector(16 downto 0);
sa: out std_ulogic;
sb: out std_ulogic;
over: inout std_ulogic
);
end center;
architecture behavior of center is
signal direction : integer range 0 to 2;
signal num : integer range -1 to 17;
begin
process (enable,ca,cb,a,b,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif enable = '1' and rising_edge(clk) then
if direction = 2 then
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
elsif direction = 0 and num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 1 and num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
elsif direction = 0 and num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end process;
end architecture behavior;
But I get a error:
signal parameter in a subprogram is not supported
I am confused, I don't know why I get this error.
I think as David also said you need to provide more information.
What it looks like for me is that your are writing a test bench the above code cannot be synthesized correctly. ISE will tell you that your syntax is ok but the delays are ignored IE the after keyword. The after keyword is only used in simulation.
That said i would also clean up the code there are a lot of redundancies. FX
The last two elsif statements. only one is needed. and the sensitivity list. only clk and enable should be there.
I've tried to clean up your code:
process (enable,clk)
begin
if enable = '0' then
over <= '0';
sa <= '0';
sb <= '0';
elsif rising_edge(clk) then
case( direction ) is
when 0 =>
if num > 0 then
if b = '1' then
if num < 2 then
num <= num - 1;
direction <= 1;
else
direction <= 2;
sa <= '1' after 10 ns;
sb <= '0' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
elsif num = -1 then
num <= 8;
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
when 1 =>
if num <= 16 then
if a = '1' then
if num >= 14 then
num <= num + 1;
direction <= 2;
else
direction <= 2;
sa <= '0' after 10 ns;
sb <= '1' after 10 ns;
over <= not over after 10 ns;
end if;
end if;
end if;
when 2 =>
if ca = '1' then
direction <= 0;
num <= 1;
elsif cb = '1' then
direction <= 1;
num <= 16;
else
direction <= 2;
num <= 8;
end if;
when others => NULL;
end case ;
end if;
end process;
Try and remove your after keywords and see if it will compile then.
i have a problem with my code it supposed to count from 0 to 99 but the problem that i have is that the counter starts at "80" and the Left number only increments at 10 seconds so it repeats..
Something like this
Starts at: 80 81 82 83 84 04 05 06 07 08 09
My code is this:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity ContadorExamen is
port(
CLK : in std_logic; -- se le asigna el pin 12
--clk1hz : out std_logic ;-- se le asigna el pin 51
datos : out std_logic_vector (6 downto 0);
unidades : out std_logic;
decenas: out std_logic
);
end entity;
architecture BH_Examen2Parcial of ContadorExamen is
signal freq1 : integer range 0 to 5000 := 0;
signal freqDec : integer range 0 to 24999999 := 0;
signal freq100 : integer range 0 to 249999999 := 0;
signal tmp1 : std_logic := '0';
signal tmp100 : std_logic := '0';
signal tmpDec : std_logic := '0';
signal counterUnidades : integer range 0 to 10 := 0;
signal counterDecenas : integer range 0 to 10 := 0;
signal segDecenas : std_logic_vector(6 downto 0);
signal segUnidades : std_logic_vector(6 downto 0);
begin
process(CLK) is
begin
if(CLK'event and CLK = '1') then
if(freq1 >= 5000) then
freq1 <= 0;
tmp1 <= not tmp1;
else
freq1 <= freq1 + 1;
tmp1 <= tmp1;
end if;
if(freq100 >= 249999999) then
freq100 <= 0;
tmp100 <= not tmp100;
else
freq100 <= freq100 + 1;
tmp100 <= tmp100;
end if;
if(freqDec >= 24999999) then
freqDec <= 0;
tmpDec <= not tmpDec;
else
freqDec <= freqDec + 1;
tmpDec <= tmpDec;
end if;
end if;
end process;
-- principio de cambios en el programa
process(tmp1) is
begin
if(tmp1 = '1') then
unidades <= '0';
decenas <= '1';
datos <= segDecenas;
else
datos <= SegUnidades;
decenas <= '0';
unidades <= '1';
end if;
end process;
ParaContarUnidades:process(tmp100) is
begin
if (tmp100 = '1') then
if(counterUnidades = 0) then
segUnidades <= "0000001";
elsif (counterUnidades = 1 ) then
segUnidades <= "1001111";
elsif (counterUnidades = 2 ) then
segUnidades <= "0010010";
elsif (counterUnidades = 3 ) then
segUnidades <= "0000110";
elsif (counterUnidades = 4 ) then
segUnidades <= "1001100";
elsif (counterUnidades = 5 ) then
segUnidades <= "0100100";
elsif (counterUnidades = 6 ) then
segUnidades <= "1100000";
elsif (counterUnidades = 7 ) then
segUnidades <= "0001111";
elsif (counterUnidades = 8 ) then
segUnidades <= "0000000";
elsif (counterUnidades = 9) then
segUnidades <= "0001100";
else
segUnidades <= "1111111";
end if;
if(counterUnidades < 9) then
counterUnidades <= counterUnidades + 1;
else
counterUnidades <= 0;
end if;
end if;
end process;
ParaContarDecenas:process(tmpDec) is
begin
if (tmpDec = '1') then
if(counterDecenas = 0) then
segDecenas <= "0000001";
elsif (counterDecenas = 1 ) then
segDecenas <= "1001111";
elsif (counterDecenas = 2 ) then
segDecenas <= "0010010";
elsif (counterDecenas = 3 ) then
segDecenas <= "0000110";
elsif (counterDecenas = 4 ) then
segDecenas <= "1001100";
elsif (counterDecenas = 5 ) then
segDecenas <= "0100100";
elsif (counterDecenas = 6 ) then
segDecenas <= "1100000";
elsif (counterDecenas = 7 ) then
segDecenas <= "0001111";
elsif (counterDecenas = 8 ) then
segDecenas <= "0000000";
elsif (counterDecenas = 9) then
segDecenas <= "0001100";
else
segDecenas <= "1111111";
end if;
if(counterDecenas < 9) then
counterDecenas <= counterDecenas + 1;
else
counterDecenas <= 0;
end if;
end if;
end process;
end architecture;
A couple issues that you will want to look into:
Note that counterDecenas and counterUnidades should be in the sensitivity list of the processes that use them because (as written) you want your segUnidades and segDecenas signals to update when tmpDec or tmp100 remain '1' but the counters change.
Moreover, you assign the counters to values based on themselves (such as counterDecenas <= counterDecenas + 1;) outside of a clocked process - this will produce a combinatorial loop. These need to be triggered only on clock edges.
Beyond that, it isn't clear what this entity is supposed to do. You say it is supposed to count from 0 to 99, but this clearly does more than the 1-liner that it would take to implement what you've described the desired functionality to be.
Whenver I try to synthesize my code, it is caught in an infinite loop i.e it is stuck at HDL SYNTHESIS. I have not used any loops. But problem persists.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mat is
port(
start,clck,start4,add4,check4,delete3,start3,add3,final3,load,load3,load4,search3:in std_logic;
data1,data2,newitem:in std_logic_vector(0 to 8);
completeload4tocontroller,completeadd3,search3cmplt,completeload3tocontroller,
completeloadtocontroller,discerncomplete,complete4add,completedel3,step4comptocntrl:out bit;
data4,data6:out std_logic_vector(0 to 15));
end mat;
architecture Behavioral of mat is
type positiveelem is array (0 to 255) of std_logic_vector(0 to 18);
type negativeelem is array (0 to 255) of std_logic_vector(0 to 18);
signal poselem:positiveelem ;
signal negelem:negativeelem ;
signal pospointer:integer range 0 to 255:=0;
signal negpointer:integer range 0 to 255:=0;
signal jpst:integer range 0 to 255 := 0;
signal jnst:integer range 0 to 255 := 0;
signal jp1st:integer range 0 to 255 := 0;
signal jp2st:integer range 0 to 255 := 0;
signal jn4st:integer range 0 to 255 := 0;
signal jp4st:integer range 0 to 255 := 0;
signal j3pntr:integer range 0 to 255 := 0;
signal j3npntr:integer range 0 to 255 := 0;
signal j3ptr:integer range 0 to 255 := 0;
type list12 is array(0 to 65535) of integer range 0 to 31;
signal clist:list12;
signal limitcount:integer range 0 to 255 :=0;
signal flag1:std_logic :='0';
signal position:integer range 0 to 255;
begin
P1:process(load,load4,clck,load3,check4,start,add4,start4,start3,delete3,add3)
variable temp4:std_logic_vector(0 to 15);
variable temp5:std_logic_vector(0 to 15);
variable temp1:std_logic_vector(0 to 15);
variable tempp3:std_logic_vector(0 to 15);
begin
if(rising_edge(clck))then
if(load='1')then
poselem(pospointer) <= data1;
negelem(negpointer) <= data2;
pospointer <= pospointer + 1;
negpointer <= negpointer + 1;
limitcount <= limitcount + 1;
if(limitcount = 10)then
completeloadtocontroller <= '1';
end if;
elsif((load4 = '1') and (load ='0'))then
poselem(pospointer) <= newitem;
pospointer <= pospointer + 1;
completeload4tocontroller <= '1';
elsif((load3 = '1') and (load = '0'))then
negelem(negpointer) <= newitem;
negpointer <= negpointer + 1;
completeload3tocontroller <= '1';
elsif(start = '1')then
if((jpst <= pospointer) and (jnst <= negpointer))then
temp4 := poselem(jpst)(0 to 15) xor negelem(jnst)(0 to 15);
clist(conv_integer(temp4)) <= clist(conv_integer(temp4)) + 1;
if((jnst = (negpointer - 1)) and (jpst < (pospointer - 1)))then
jnst <= 0;
jpst <= jpst + 1;
elsif(jnst < (negpointer - 1) and (jpst < (pospointer - 1)))then
jnst <= jnst + 1;
elsif(jpst = (pospointer - 1) and (jnst < (negpointer - 1)))then
jnst <= jnst + 1;
elsif((jp1st = pospointer) and (jp2st = pospointer) and
(jpst = pospointer) and (jnst = negpointer))then
discerncomplete <= '1';
end if;
end if;
elsif(start4 = '1')then
if(add4 = '1')then
temp1 := newitem(0 to 15) xor negelem(jn4st)(0 to 15);
if(clist(conv_integer(temp1)) = 0)then
data4 <= temp1;
end if;
clist(conv_integer(temp1)) <= clist(conv_integer(temp1)) + 1;
if(jn4st < (negpointer - 1))then
jn4st <= jn4st + 1;
elsif((jp4st = pospointer - 1) and (jn4st = negpointer - 1))then
complete4add <= '1';
end if;
end if;
elsif(start3 = '1')then
if(delete3 = '1')then
if((poselem(position)(0 to 15) /= poselem(j3pntr))
and (poselem(position)(16 to 18) /= poselem(j3pntr)(16 to 18)))then
tempp3 := poselem(position)(0 to 15) xor poselem(j3pntr)(0 to 15);
if(clist(conv_integer(tempp3)) = 1)then
data6 <= tempp3;
end if;
if(clist(conv_integer(tempp3)) /= 0)then
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) - 1;
end if;
if(j3pntr < (pospointer - 1))then
j3pntr <= j3pntr + 1;
elsif((j3pntr = pospointer - 1) and (j3npntr = negpointer - 1))then
completedel3 <= '1';
poselem(position) <= "0000000000000000000";
end if;
end if;
elsif(search3 = '1')then
if((poselem(position)(16 to 18) /= newitem(16 to 18))
and (poselem(position)(0 to 15) = newitem(0 to 15)))then
flag1 <= '1';
end if;
if((position < pospointer) and (flag1 = '0'))then
position <= position + 1;
elsif(flag1 = '1')then
search3cmplt <= '1';
end if;
elsif(add3 = '1')then
tempp3 := newitem(0 to 15) xor poselem(j3ptr)(0 to 15);
if(clist(conv_integer(tempp3)) = 0)then
data4 <= tempp3;
end if;
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) + 1;
if(j3ptr < pospointer - 1 and (j3ptr = (position - 1)))then
j3ptr <= j3ptr + 2;
elsif(j3ptr = (pospointer - 1))then
completeadd3 <= '1';
else
j3ptr <= j3ptr + 1;
end if;
end if;
end if;
end if;
if(falling_edge(clck))then
if(start = '1')then
if((jp1st /= pospointer) and (jp2st /= pospointer) and (poselem(jp1st)(16 to 18) /= poselem(jp2st)(16 to 18))
and (poselem(jp1st)(0 to 15) /= poselem(jp2st)(0 to 15))) then
temp5 := poselem(jp1st)(0 to 15) xor poselem(jp2st)(0 to 15);
clist(conv_integer(temp5)) <= clist(conv_integer(temp5)) + 1;
end if;
if(jp1st < (pospointer - 1) and jp2st = (pospointer-1))then
jp1st <= jp1st + 1;
jp2st <= 0;
elsif(jp1st = (pospointer - 1) and jp2st < (pospointer-1))then
jp2st <= jp2st + 1;
elsif(jp1st < (pospointer - 1) and jp2st < (pospointer-1))then
jp2st <= jp2st + 1;
elsif((jp1st = pospointer) and (jp2st = pospointer) and (jpst = pospointer) and (jnst = negpointer))then
discerncomplete <= '1';
end if;
elsif(start4 = '1')then
if(add4 = '1')then
if((poselem(jp4st)(0 to 15) /= "0000000000000000"))then
if(poselem(jp4st)(0 to 15) /= newitem(0 to 15))
and (poselem(jp4st)(16 to 18) /= newitem(16 to 18)))then
temp1 := newitem(0 to 15) xor poselem(jp4st)(0 to 15);
if(clist(conv_integer(temp1)) = 0)then
data4 <= temp1;
end if;
clist(conv_integer(temp1)) <= clist(conv_integer(temp1)) + 1;
end if;
if(jp4st < (pospointer - 1))then
jp4st <= jp4st + 1;
elsif((jp4st = pospointer - 1) and (jn4st = negpointer - 1))then
complete4add <= '1';
end if;
end if;
elsif(start3 = '1')then
if(delete3 = '1')then
tempp3 := newitem(0 to 15) xor negelem(j3npntr)(0 to 15);
if(clist(conv_integer(tempp3)) = 1)then
data6 <= tempp3;
end if;
if(clist(conv_integer(tempp3)) = 0)then
clist(conv_integer(tempp3)) <= clist(conv_integer(tempp3)) - 1;
end if;
if(j3npntr < negpointer - 1 )then
j3npntr <= j3npntr + 1;
elsif((j3pntr = pospointer - 1) and (j3npntr = negpointer - 1))then
completedel3 <= '1';
poselem(position) <= "0000000000000000000";
end if;
end if;
end if;
end if;
end process P1;
end Behavioral;
My comments address some of these issues, but I thought I'd type them up as an answer to add a little more detail and clarification.
Synthesis software getting stuck at a certain step and locking up has little to nothing to do with any particular language structure you're using, and probably means the software is having trouble parsing your code. While I would call this a bug in the software, you can probably get around it by looking for syntax errors (using another compiler, like ModelSim or something, might also help, if you have access). For instance, you appear to have an if-loop you're not closing somewhere under if falling_edge(clck). You also have a missing ( on the lines:
if(poselem(jp4st)(0 to 15) /= newitem(0 to 15))
and (poselem(jp4st)(16 to 18) /= newitem(16 to 18)))then
And you're assigning data1, a 9-bit vector, to poselem(pospointer), a 19-bit vector (and other similar assignments). Check your port and signal definitions.