I've got a problem with a synthesis of that code.
The error which is shown is "Signal blk_pointer cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.".
I want to save communication messages between two devices. The part with falling_edge and rising_edge is to find a current part of message, and create a pointer to that part (msg_pointer, blk_pointer). Then I want to save the current value to a buffer.
It works when I delete the last part ( that with for loop).
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable buf_pointer : INTEGER range 0 to 13:=0; --pointing to a number of bit in the output S14T7C7_TEMP buf
variable S14T7C7_TEMP : STD_LOGIC_VECTOR (13 downto 0):="00000000000000";
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if falling_edge(com_delayed) then
if com_level_time > 4500 then
msg_pointer := 0;
blk_pointer := 0;
buf_pointer := 0;
elsif ( com_level_time < 4500 ) and ( com_level_time > 630 ) then
msg_pointer := 1;
blk_pointer := 0;
buf_pointer := 0;
elsif blk_pointer >= 9 then
blk_pointer:=0;
if msg_pointer<6 then
msg_pointer:=msg_pointer+1;
end if;
elsif com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
njed:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
njed:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
njed:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
njed:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
njed:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
njed:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
njed:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
njed:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
njed:=9;
copy:='1';
end if;
end if;
if rising_edge(com_delayed) then
if com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
nzer:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
nzer:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
nzer:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
nzer:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
nzer:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
nzer:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
nzer:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
nzer:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
nzer:=9;
copy:='1';
end if;
end if;
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
if copy='1' then
For it in 1 to 9 loop
if nzer/=0 then
message1(msg_pointer_ext)(blk_pointer_ext-nzer):='0';
nzer:=nzer-1;
end if;
end loop;
end if;
copy:='0';
end process;
New two processes:
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if rising_edge(com_delayed) then
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
nzer:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
nzer:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
nzer:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
nzer:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
nzer:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
nzer:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
nzer:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
nzer:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
nzer:=9;
copy:='1';
end if;
if copy='1' then
For it in 1 to 9 loop
if nzer/=0 then
message1(msg_pointer)(blk_pointer-nzer):='0';
nzer:=nzer-1;
end if;
end loop;
end if;
copy:='0';
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
end process;
process(com_delayed)
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
variable nzer : INTEGER range 0 to 9:=0;
variable njed : INTEGER range 0 to 9:=0;
variable copy : STD_LOGIC;
begin
if falling_edge(com_delayed) then
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if com_level_time > 4500 then
msg_pointer := 0;
blk_pointer := 0;
elsif ( com_level_time < 4500 ) and ( com_level_time > 630 ) then
msg_pointer := 1;
blk_pointer := 0;
elsif blk_pointer >= 9 then
blk_pointer:=0;
if msg_pointer<6 then
msg_pointer:=msg_pointer+1;
end if;
elsif com_level_time <= 80 then
blk_pointer:=blk_pointer+1;
njed:=1;
copy:='1';
elsif (com_level_time>80 and com_level_time<=142) then
blk_pointer:=blk_pointer+2;
njed:=2;
copy:='1';
elsif (com_level_time>142 and com_level_time<=200) then
blk_pointer:=blk_pointer+3;
njed:=3;
copy:='1';
elsif (com_level_time>200 and com_level_time<=274) then
blk_pointer:=blk_pointer+4;
njed:=4;
copy:='1';
elsif (com_level_time>274 and com_level_time<=336) then
blk_pointer:=blk_pointer+5;
njed:=5;
copy:='1';
elsif (com_level_time>336 and com_level_time<=396) then
blk_pointer:=blk_pointer+6;
njed:=6;
copy:='1';
elsif (com_level_time>396 and com_level_time<=460) then
blk_pointer:=blk_pointer+7;
njed:=7;
copy:='1';
elsif (com_level_time>460 and com_level_time<=526) then
blk_pointer:=blk_pointer+8;
njed:=8;
copy:='1';
elsif (com_level_time>526 and com_level_time<=630) then
blk_pointer:=blk_pointer+9;
njed:=9;
copy:='1';
end if;
if copy='1' then
For it in 1 to 9 loop
if njed/=0 then
message1(msg_pointer)(blk_pointer-njed):='0';
njed:=njed-1;
end if;
end loop;
end if;
copy:='0';
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
end process;
Next error is : Multi-Source on Integers in concurrent assignment. (external pointers)
And new version without errors:
process(clk_com, com_ecu38)
variable com_clear : STD_LOGIC:='0';
variable tclt : INTEGER range 0 to 32000:=0;
begin
if rising_edge(clk_com) and tclt /= 31999 then
tclt := tclt +1;
end if;
if com_ecu38'event then
com_level_time:=tclt;
com_clear:='1';
end if;
if com_clear='1' then
tclt:=0;
com_delayed<=com_ecu38;
end if;
com_clear:='0';
end process;
process(com_delayed)
begin
if rising_edge(com_delayed) then
if com_level_time>20 and com_level_time<=80 then
nzer:=1;
elsif (com_level_time>80 and com_level_time<=142) then
nzer:=2;
elsif (com_level_time>142 and com_level_time<=200) then
nzer:=3;
elsif (com_level_time>200 and com_level_time<=274) then
nzer:=4;
elsif (com_level_time>274 and com_level_time<=336) then
nzer:=5;
elsif (com_level_time>336 and com_level_time<=396) then
nzer:=6;
elsif (com_level_time>396 and com_level_time<=460) then
nzer:=7;
elsif (com_level_time>460 and com_level_time<=526) then
nzer:=8;
elsif (com_level_time>526 and com_level_time<=630) then
nzer:=9;
else
nzer:=0;
end if;
copy0<=not(copy0);
end if;
end process;
process(com_delayed)
begin
if falling_edge(com_delayed) then
if com_level_time > 4500 then
njed:=12;
elsif com_level_time > 630 and com_level_time <= 4500 then
njed:=11;
elsif com_level_time>20 and com_level_time<=80 then
njed:=1;
elsif (com_level_time>80 and com_level_time<=142) then
njed:=2;
elsif (com_level_time>142 and com_level_time<=200) then
njed:=3;
elsif (com_level_time>200 and com_level_time<=274) then
njed:=4;
elsif (com_level_time>274 and com_level_time<=336) then
njed:=5;
elsif (com_level_time>336 and com_level_time<=396) then
njed:=6;
elsif (com_level_time>396 and com_level_time<=460) then
njed:=7;
elsif (com_level_time>460 and com_level_time<=526) then
njed:=8;
elsif (com_level_time>526 and com_level_time<=630) then
njed:=9;
else
njed:=0;
end if;
copy1<=not(copy1);
end if;
end process;
process(copy1, copy0)
variable n : INTEGER range 0 to 9:=0;
variable bit_to_write : STD_LOGIC;
variable inc_msg : STD_LOGIC;
variable c1 : STD_LOGIC;
variable c0 : STD_LOGIC;
variable msg_pointer : INTEGER range 0 to 20:=0; --pointing to a number of message block
variable blk_pointer : INTEGER range 0 to 50:=0; --pointing to a number of bit from the current block
begin
if copy1'event then
n:=njed;
c1:='1';
elsif copy0'event then
n:=nzer;
c0:='1';
end if;
msg_pointer:=msg_pointer_ext;
blk_pointer:=blk_pointer_ext;
if c1='1' then
bit_to_write:='1';
elsif c0='1' then
bit_to_write:='0';
end if;
if n=12 then
msg_pointer:=0;
blk_pointer:=0;
com_ch_out<=not(com_ch_out);
elsif n=11 then
msg_pointer:=1;
blk_pointer:=0;
else
if blk_pointer + n <9 then
blk_pointer:=blk_pointer+n;
else
n:=9-blk_pointer;
inc_msg:='1';
blk_pointer:=9;
end if;
For it in 1 to 9 loop
if n/=0 then
message1(msg_pointer)(blk_pointer-n):=bit_to_write;
n:=n-1;
end if;
end loop;
end if;
if inc_msg='1' then
if msg_pointer<5 then
blk_pointer_ext:=0;
msg_pointer_ext:=msg_pointer+1;
end if;
else
msg_pointer_ext:=msg_pointer;
blk_pointer_ext:=blk_pointer;
end if;
n:=0;
inc_msg:='0';
c1:='0';
c0:='0';
end process;
process(com_ch_out)
begin
if com_ch_out'event then
if latch_outputs='0' then
if stc_decide = '0' then
S14T7C7(0)<=message1(1)(1);
S14T7C7(1)<=message1(1)(2);
S14T7C7(2)<=message1(1)(3);
S14T7C7(3)<=message1(1)(4);
S14T7C7(4)<=message1(1)(5);
S14T7C7(5)<=message1(1)(6);
S14T7C7(6)<=message1(1)(7);
S14T7C7(7)<=message1(2)(1);
S14T7C7(8)<=message1(2)(2);
S14T7C7(9)<=message1(2)(3);
S14T7C7(10)<=message1(2)(4);
S14T7C7(11)<=message1(2)(5);
S14T7C7(12)<=message1(2)(6);
S14T7C7(13)<=message1(2)(7);
else
S14T7C7(0)<=message1(4)(1);
S14T7C7(1)<=message1(4)(2);
S14T7C7(2)<=message1(4)(3);
S14T7C7(3)<=message1(4)(4);
S14T7C7(4)<=message1(4)(5);
S14T7C7(5)<=message1(4)(6);
S14T7C7(6)<=message1(4)(7);
S14T7C7(7)<=C7I(0);
S14T7C7(8)<=C7I(1);
S14T7C7(9)<=C7I(2);
S14T7C7(10)<=C7I(3);
S14T7C7(11)<=C7I(4);
S14T7C7(12)<=C7I(5);
S14T7C7(13)<=C7I(6);
end if;
end if;
end if;
end process;
strong text
Related
I'm working on digital clock using VHDL Altera board. And I've got stuck during coding. I was trying to make a digital clock that shows hours, minutes, and seconds on six 7-segments. My code is like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_main is
port(clk_50mhz, reset, min_sw, hour_sw: in std_logic;
fnd_s: out std_logic_vector(5 downto 0);
fnd_d: out std_logic_vector(7 downto 0));
end time_main;
architecture clock of time_main is
signal clk_cnt: integer range 0 to 50000000;
signal data1, data3, data5, temp: integer range 0 to 9;
signal data2, data4: integer range 0 to 5;
signal data6: integer range 0 to 2;
signal cnt: integer range 0 to 5;
signal clk_test: integer range 0 to 5000000000;
variable decode_seg: std_logic_vector(7 downto 0);
begin
case count_seg is
when 0 => decode_seg := "00111111";
when 1 => decode_seg := "00000110";
when 2 => decode_seg := "01011011";
when 3 => decode_seg := "01001111";
when 4 => decode_seg := "01100110";
when 5 => decode_seg := "01101101";
when 6 => decode_seg := "01111101";
when 7 => decode_seg := "00100111";
when 8 => decode_seg := "01111111";
when 9 => decode_seg := "01101111";
when others => decode_seg := "00000000";
end case;
return(decode_seg);
end dis_7_seg;
begin
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
sec_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data1 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
data1 <= 0;
else
data1 <= data1 + 1;
end if;
end if;
end if;
end process;
sec_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data2 <= 0;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9) then
if(data2 = 5) then
data2 <= 0;
else
data2 <= data2 + 1;
end if;
end if;
end if;
end if;
end process;
min_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data3 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5) then
if(data3 = 9) then
data3 <= 0;
else
data3 <= data3 + 1;
end if;
end if;
end if;
end if;
end process;
min_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data4 <= 0;
elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
if(clk_cnt = 50000000) then
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9) then
if(data4 = 5) then
data4 <= 0;
else
data4 <= data4 + 1;
end if;
end if;
end if;
end if;
end if;
end process;
hour_1: process(clk_50mhz, reset)
begin
if(reset = '0') then
data5 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9) then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data5 <= 0;
elsif(data5 = 9)then
data5 <= 0;
else
data5 <= data5 + 1;
end if;
end if;
end if;
end if;
end process;
hour_10: process(clk_50mhz, reset)
begin
if(reset = '0') then
data6 <= 0;
elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then
if(clk_cnt = 50000000) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
elsif(clk_50mhz'event and clk_50mhz = '1') then -
if(clk_cnt = 50000000) then
if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
if(data5 = 3 and data6 = 2) then
data6 <= 0;
elsif(data5 = 9) then
data6 <= data6 + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50mhz)
begin
if(clk_50mhz'event and clk_50mhz = '1') then
if(clk_test = 5000000000) then
clk_test <= 0;
else
clk_test <= clk_test + 1;
end if;
end if;
end process;
process(clk_test)
begin
if(clk_test = 5000000000) then
if(cnt = 5) then
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process;
process(data1, data2, data3, data4, data5, data6, cnt)
begin
If (cnt=0) then
fnd_s <= "000001";
temp <= data1;
else if(cnt=1) then
fnd_s <= "000010";
temp <= data2;
else if (cnt=2) then
fnd_s <= "000100";
temp <= data3;
else if (cnt=3) then
fnd_s <= "001000";
temp <= data4;
else if (cnt=4) then
fnd_s <= "010000";
temp <= data5;
else if (cnt=5) then
fnd_s <= "100000";
temp <= data6;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
fnd_d <= dis_7_seg(temp);
end clock;
========================================================================
however, the i found out that the first segment did not show anything, just total OFF... and I found that other 5 segments show the same number: from 0 to 9 for 9 seconds, and then the segments show 0 again and keep counting from 0 to 9. I thought I made a good code enough to make hours, minutes, and seconds... but it shows only seconds.... Can anyone tell me what's wrong with my code.. please?
i'm working on a project using vhdl to configure a fpga board spartan 3E. what i have to do is a genius puzzle, in my main code there is a state machine to control the logic.
everything works well when i simulate the code using xilinx simulator but when i run the .bit file to the FPGA board what happens is that the first led of the sequence turns on and then turns off, this should happen but then when i click the right button it just stop working and the next sequence is never shown.
of course there is a issue of deboucing the buttons, and that's the reason i'm using a counter to prevent the repic to bug the system.
i'm working hard on this code to function but this issue doesn't go away, maybe i'm doing something wrong i don't know or i'm not doing something i should.
here is my main code, which is the state machine and a clock proccess with the counter.
Flag_conte = starts ou blocks the counter
Flag_estou_contando = 1=counting, 0= not counting, 3= just finished count.
BCD = board buttons IN
LEDs = corresponds to 4 leds that will show the sequence in the game
entity Algoritmo is
port(
clk: in std_logic;
BCD: in std_logic_vector (3 downto 0);
botaoStart: in std_logic;
botaoReset: in std_logic;
seven_seg: out std_logic_vector(6 downto 0);
anode: out std_logic_vector(3 downto 0);
LEDS: out std_logic_vector(3 downto 0)
);
END Algoritmo;
architecture Behavioral of Algoritmo is
subtype state_type is integer range 5 downto 0;
signal state, nextstate: state_type:=0;
signal Inicio, nclk: std_logic:= '0';
--variable posicaoAtual: integer :=0;
type mem1 is array (0 to 13) of std_logic_vector (3 downto 0);
constant vetorSequencia: mem1 := ( "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010", "0100", "1000", "0001", "0010");
constant generic1hz: integer:= 12_500_000;
signal t3count:integer:=0;
signal posA, posB, signalScore, Flag_conte,
Flag_estou_contando:integer:=0;
signal valor: integer :=12_500_000;
Begin
-------------
process (state,BCD,botaoStart,Flag_estou_contando)
variable Pos: integer :=0;
variable score: integer:=0;
variable posicaoAtual: integer:=0;
variable tentativa: std_logic_vector (3 downto 0);
begin
case state is
when 0 => if (botaoStart = '0')
then nextstate <= 0;-- estado idle, esperando entrada do tclado,led1=1;
else nextstate <= 1;
end if;
when 1 =>-- if(Flag_estou_contando =0)then
if(nextstate=2)then
Flag_conte <=0;
nextstate <= 2;
else if (nextstate/=2)then
if (posicaoAtual < score)then
if(Flag_estou_contando=0)then
LEDS <= vetorSequencia(posicaoAtual);
posA <= posicaoAtual;
Flag_conte<=1;
valor<=10_000_000;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
else if (Flag_estou_contando=3)then
--posicaoAtual:=0;
posicaoAtual := posicaoAtual + 1;
posA <= posicaoAtual;
nextstate <=1;
Flag_conte<=0;
end if;end if;end if;
else if(posicaoAtual = score)then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=10_000_000;
-- posicaoAtual :=0;
posA <= posicaoAtual;
else if(Flag_estou_contando=1)then
LEDS <=vetorSequencia(posicaoAtual);
nextstate<=1;
else if(Flag_estou_contando=3)then
posicaoAtual:=0;
posA <= posicaoAtual;
Flag_conte<=0;
nextstate <= 2;
end if;end if;end if;
end if;end if;
Flag_conte <=1;
end if;end if;
when 2 => --if(Flag_estou_contando=0)then
if (BCD = "0000")then
if(Flag_estou_contando=0)then
LEDS <= "0000"; --nextstate <= 2;
else if (Flag_estou_contando=1)then
nextstate<=2;
else if (Flag_estou_contando=3)then
Flag_conte <= 0;
nextstate<=3;
end if;end if;end if;
else if(BCD /= "0000")then
if(Flag_estou_contando=0)then
Flag_conte<=1;
valor<=200_000_000;
tentativa := BCD;
LEDS <= tentativa;
else if(Flag_estou_contando=3)then
nextstate <= 3;
else if(Flag_estou_contando=1)then
LEDS <= tentativa;
nextstate <=2;
end if;end if;end if;
end if;end if;
when 3 => if (vetorSequencia(Pos) = tentativa)then
if (Pos < score)then
nextstate <= 2;
Pos := Pos + 1;
posB <= Pos;
else if(Pos = score)then
score := score + 1;
signalScore <= score;
nextstate <= 1;
Pos := 0;
if (score = 15)-- if score =15 finish game
then nextstate <= 5;
end if;--end if
end if;end if;
else -- se estiver errado, perde o jogo
nextstate <= 4; -- goes to game over
end if;
when 4 => if (botaoReset = '1') -- game over
then nextstate <= 4;-- "U LOST nOOB"
elsif (botaoReset = '0')
then nextstate <= 0; --
end if;
when 5 => if (botaoReset = '1') -- jogo ganho
then nextstate <= 5; -- "GG"
elsif (botaoReset = '0')
then nextstate <= 0;
end if;
end case;
end process;
process (clk, Flag_conte)
variable sum, count :integer:=0;
begin
if rising_edge(clk) then
if(Flag_estou_contando = 0) then
if (Flag_conte = 1) then
count :=0;
Flag_estou_contando <=1;
end if;
end if;
if(Flag_estou_contando=3) then
if(Flag_conte =0)then
Flag_estou_contando <= 0;
else
Flag_estou_contando <=3;
end if;
end if;
if (Flag_estou_contando =1)then
if(count < valor)then
count := count + 1;
else
count:=0;
Flag_estou_contando <=3;
end if;
end if;
sum := sum +1;
if(sum = generic1hz)then -- 1hz generate
state <= nextstate;
nclk <= not nclk;
sum := 0;--restart count for 1hz generate
end if;
end if;
end process;
end Behavioral;
if i wasnt clear, please let me know i will try to explain better, if anyone could help i would be very greatful, thank you for your time.
You should try post place & route simulation to verify whats happen:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_simulate_post_place.htm
With some family device you can use chipscope technology to debug:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm
Sorry for my English.
Regards.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fsm is
Port ( clock : in STD_LOGIC;
P : in STD_LOGIC_VECTOR(4 downto 0);
reset : in STD_LOGIC;
State : out STRING);
end fsm;
architecture Behavioral of fsm is
TYPE State_type IS (Initial, Starting,Closed,Closing,Stopped,Stopping,Req_sent,Opened,Ack_sent,Ack_rcvd); -- Define the states
SIGNAL State : State_Type; -- Create a signal that begin
begin
PROCESS (clock,reset)
BEGIN
If (reset = "1") THEN
State <= Initial;
ELSE IF rising_edge(clock) THEN -- if there is a rising edge
-- clock, then do the stuff below
-- The CASE statement checks the value of the State
-- and based on the value and any other control signals, --change s to a new state.
CASE State IS
WHEN Initial =>
IF P="00000" THEN
State <= Closed;
ELSIF P="00010" THEN
State<=Starting;
ELSIF P="00011" THEN
State<=Initial ;
END IF;
WHEN Starting =>
IF P <="00000" THEN
State <= Req_sent;
ELSIF P <="00010" THEN
State<=Starting;
END IF;
WHEN Closed =>
IF P <="00010" THEN
State <= Req_sent;
ELSIF P <="00001" THEN
State<=Initial;
ELSIF P <="00100" THEN
State<=Closed;
END IF;
WHEN Stopped=>
IF P <="00110" THEN
State <= Stopped;
ELSIF P <="00011" THEN
State <=Closed ;
ELSIF P <="00001" THEN
State<=Starting;
ELSIF P <="01101" THEN
State<=Req_sent;
ELSIF P <="01100" THEN
State<=Ack_sent;
END IF;
WHEN Closing =>
IF P <="00101" THEN
State <= Closing;
ELSIF P <="00001" THEN
State<=Initial;
ELSIF P <="01110" THEN
State<=Closed;
ELSIF P <="00010" THEN
State<=Stopping;
END IF;
WHEN Req_sent=>
IF P <="01001" THEN
State<=Req_sent;
ELSIF P <="01101" THEN
State<=Opened;
ELSIF P <="01100" THEN
State<=Ack_sent;
ELSIF P <="10000" THEN
State<=Ack_rcvd;
ELSIF P <="10011" THEN
State<=Stopped;
ELSIF P <="00001" THEN
State<=Starting;
ELSIF P <="00011" THEN
State<=Closing;
END IF;
WHEN Stopping=>
IF P <="00111" THEN
State<=Stopping;
ELSIF P <="00011" THEN
State<=Closing;
ELSIF P <="01110" THEN
State<=Stopped;
ELSIF P <="00001" THEN
State<=Starting;
END IF;
WHEN Opened=>
IF P <="01000" THEN
State<=Opened;
ELSIF P <="00001" THEN
State<=Starting;
ELSIF P <="00011" THEN
State<=Closing;
ELSIF P <="01111" THEN
State<=Stopping;
ELSIF P <="01100" THEN
State<=Ack_sent;
END IF;
WHEN Ack_sent=>
IF P <="01010" THEN
State<=Ack_sent;
ELSIF P <="00011" THEN
State<=Closing;
ELSIF P <="10000" THEN
State<=Opened;
ELSIF P <="10010" THEN
State<=Red_sent;
ELSIF P <="00001" THEN
State<=Starting;
ELSIF P <="10011" THEN
State<=Stopped;
END IF;
WHEN Ack_rcvd=>
IF P <="01011" THEN
State<=Ack_rcvd;
ELSIF P <="10000" THEN
State<=Opened;
ELSIF P <="00011" THEN
State<=Closing;
ELSIF P <="10001" THEN
State<=Req_sent;
ELSIF P="10011" THEN
State<=Stopped;
ELSIF P <="00001" THEN
State<=Starting;
END IF;
END CASE;
END IF;
END PROCESS;
end Behavioral;
please help me figure out the error in this code.Have been trying for hours
ERROR:HDLCompiler:806 - "C:/.Xilinx/fsm/fsm.vhd" Line 184: Syntax error near "PROCESS".
There are several errors.
Your internal signal State is a duplicate name of the entity signal State
Your check for reset uses "1", when it should be '1'
Your use of Red_sent instead of Req_sent
But the problem which is causing you the error message, is that you use ELSE IF instead of ELSIF.
I want to create dynamic string array, so I can transmit it to the lcd module on my Altera DE2-115 board. So far the most part is working, but the last part is not wrking in the following code:
CREATE_STRING: PROCESS (CLK, RESET, X)
BEGIN
IF RESET = '1' THEN
FOR i IN 0 TO 31 LOOP
lcd_data(i) <= x"30";
END LOOP;
END IF;
IF X /= 0 THEN
FOR i IN 0 TO 15 LOOP
IF X(15-i) = '0' THEN
lcd_data(i) <= x"30";
END IF;
IF X(15-i) ='1' THEN
lcd_data(i) <= x"31";
END IF;
END LOOP;
END IF;
IF char_count > 15 AND lcd_y = '1' THEN
ELSIF CLK = '1' AND CLK'event THEN
lcd_data(to_integer(char_count)) <= x"31";
END IF;
END PROCESS CREATE_STRING;
I'm getting this error message:
Error (10818): Can't infer register for "lcd_data[31][0]" at seqdec.vhd(75) because it does not hold its value outside the clock edge
for every lcd_data[31][x].
I googled the error and if I am not completly on the wrong thought I think i understood it, but I'm still not able the get it right...
Would be great if somebody could help with advice.
Best regards
Adrian
Did this change:
CREATE_STRING: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
FOR i IN 0 TO 31 LOOP
lcd_data(i) <= x"30";
END LOOP;
ELSIF CLK = '1' AND CLK'event THEN
IF X /= 0 THEN
FOR i IN 0 TO 15 LOOP
IF X(15-i) = '0' THEN
lcd_data(i) <= x"30";
END IF;
IF X(15-i) ='1' THEN
lcd_data(i) <= x"31";
END IF;
END LOOP;
END IF;
ELSIF lcd_y = '1' THEN
lcd_data(to_integer(pos_count)) <= x"31";
END IF;
END PROCESS CREATE_STRING;
But still the same problem.
To properly describe a register, you must reverse the order of the if statements as follows:
CREATE_STRING: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
FOR i IN 0 TO 31 LOOP
lcd_data(i) <= x"30";
END LOOP;
ELSIF CLK = '1' AND CLK'event THEN
IF X /= 0 THEN
FOR i IN 0 TO 15 LOOP
IF X(15-i) = '0' THEN
lcd_data(i) <= x"30";
END IF;
IF X(15-i) ='1' THEN
lcd_data(i) <= x"31";
END IF;
END LOOP;
END IF;
IF char_count > 15 AND lcd_y = '1' THEN
lcd_data(to_integer(char_count)) <= x"31";
END IF;
END IF;
END PROCESS CREATE_STRING;
i have a problem with my code it supposed to count from 0 to 99 but the problem that i have is that the counter starts at "80" and the Left number only increments at 10 seconds so it repeats..
Something like this
Starts at: 80 81 82 83 84 04 05 06 07 08 09
My code is this:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity ContadorExamen is
port(
CLK : in std_logic; -- se le asigna el pin 12
--clk1hz : out std_logic ;-- se le asigna el pin 51
datos : out std_logic_vector (6 downto 0);
unidades : out std_logic;
decenas: out std_logic
);
end entity;
architecture BH_Examen2Parcial of ContadorExamen is
signal freq1 : integer range 0 to 5000 := 0;
signal freqDec : integer range 0 to 24999999 := 0;
signal freq100 : integer range 0 to 249999999 := 0;
signal tmp1 : std_logic := '0';
signal tmp100 : std_logic := '0';
signal tmpDec : std_logic := '0';
signal counterUnidades : integer range 0 to 10 := 0;
signal counterDecenas : integer range 0 to 10 := 0;
signal segDecenas : std_logic_vector(6 downto 0);
signal segUnidades : std_logic_vector(6 downto 0);
begin
process(CLK) is
begin
if(CLK'event and CLK = '1') then
if(freq1 >= 5000) then
freq1 <= 0;
tmp1 <= not tmp1;
else
freq1 <= freq1 + 1;
tmp1 <= tmp1;
end if;
if(freq100 >= 249999999) then
freq100 <= 0;
tmp100 <= not tmp100;
else
freq100 <= freq100 + 1;
tmp100 <= tmp100;
end if;
if(freqDec >= 24999999) then
freqDec <= 0;
tmpDec <= not tmpDec;
else
freqDec <= freqDec + 1;
tmpDec <= tmpDec;
end if;
end if;
end process;
-- principio de cambios en el programa
process(tmp1) is
begin
if(tmp1 = '1') then
unidades <= '0';
decenas <= '1';
datos <= segDecenas;
else
datos <= SegUnidades;
decenas <= '0';
unidades <= '1';
end if;
end process;
ParaContarUnidades:process(tmp100) is
begin
if (tmp100 = '1') then
if(counterUnidades = 0) then
segUnidades <= "0000001";
elsif (counterUnidades = 1 ) then
segUnidades <= "1001111";
elsif (counterUnidades = 2 ) then
segUnidades <= "0010010";
elsif (counterUnidades = 3 ) then
segUnidades <= "0000110";
elsif (counterUnidades = 4 ) then
segUnidades <= "1001100";
elsif (counterUnidades = 5 ) then
segUnidades <= "0100100";
elsif (counterUnidades = 6 ) then
segUnidades <= "1100000";
elsif (counterUnidades = 7 ) then
segUnidades <= "0001111";
elsif (counterUnidades = 8 ) then
segUnidades <= "0000000";
elsif (counterUnidades = 9) then
segUnidades <= "0001100";
else
segUnidades <= "1111111";
end if;
if(counterUnidades < 9) then
counterUnidades <= counterUnidades + 1;
else
counterUnidades <= 0;
end if;
end if;
end process;
ParaContarDecenas:process(tmpDec) is
begin
if (tmpDec = '1') then
if(counterDecenas = 0) then
segDecenas <= "0000001";
elsif (counterDecenas = 1 ) then
segDecenas <= "1001111";
elsif (counterDecenas = 2 ) then
segDecenas <= "0010010";
elsif (counterDecenas = 3 ) then
segDecenas <= "0000110";
elsif (counterDecenas = 4 ) then
segDecenas <= "1001100";
elsif (counterDecenas = 5 ) then
segDecenas <= "0100100";
elsif (counterDecenas = 6 ) then
segDecenas <= "1100000";
elsif (counterDecenas = 7 ) then
segDecenas <= "0001111";
elsif (counterDecenas = 8 ) then
segDecenas <= "0000000";
elsif (counterDecenas = 9) then
segDecenas <= "0001100";
else
segDecenas <= "1111111";
end if;
if(counterDecenas < 9) then
counterDecenas <= counterDecenas + 1;
else
counterDecenas <= 0;
end if;
end if;
end process;
end architecture;
A couple issues that you will want to look into:
Note that counterDecenas and counterUnidades should be in the sensitivity list of the processes that use them because (as written) you want your segUnidades and segDecenas signals to update when tmpDec or tmp100 remain '1' but the counters change.
Moreover, you assign the counters to values based on themselves (such as counterDecenas <= counterDecenas + 1;) outside of a clocked process - this will produce a combinatorial loop. These need to be triggered only on clock edges.
Beyond that, it isn't clear what this entity is supposed to do. You say it is supposed to count from 0 to 99, but this clearly does more than the 1-liner that it would take to implement what you've described the desired functionality to be.