Making a serial in serial out adder - vhdl

Question

I am confused about sequential logic with components (I am new).
I have these components, but I get confused how to use them within a process. I need help understanding how sequential logic works with components, also I am unsure if my input/output vectors are correct. I'm having trouble with the inputs and outputs for the shift registers, like if x(0) <= sin is the right call.
I have to design this:
(https://i.stack.imgur.com/mwVdw.jpg)
This is my main file
use IEEE.STD_LOGIC_1164.ALL;
entity sa_top is
port(
x: in STD_LOGIC_VECTOR(7 downto 0);
y: in STD_LOGIC_VECTOR(7 downto 0);
clk: in STD_LOGIC;
rst: in STD_LOGIC;
s: out STD_LOGIC_VECTOR(7 downto 0)
);
end sa_top;
architecture Behavioral of sa_top is
-- shift register
component sr is
port(
sin: in STD_LOGIC;
sout: out STD_LOGIC;
clk: in STD_LOGIC;
rst: in STD_LOGIC
);
end component sr;
-- d flip/flop
component dff is
port(
d: in STD_LOGIC;
q: in STD_LOGIC;
clk: in STD_LOGIC;
rst: in STD_LOGIC
);
end component dff;
-- full adder
component fa is
port(
a: in STD_LOGIC;
b: in STD_LOGIC;
cin: in STD_LOGIC;
sum: out STD_LOGIC;
cout: out STD_LOGIC
);
end component fa;
signal xi, yi, si: std_logic;
signal xo, yo, so: std_logic;
signal s_temp: std_logic;
signal carry: std_logic;
begin
xi <= x(0);
yi <= y(0);
inp_x_instance: sr port map(sin => xi, sout => xo, clk => clk, rst => rst);
inp_y_instance: sr port map(sin => yi, sout => yo, clk => clk, rst => rst);
adder_instace: fa port map(a => xo, b=> yo, cin => carry, sum => si, cout => carry);
op_s_instance: sr port map(sin => si, sout => so, clk => clk, rst => rst);
--df_instance: dff port map(d => s_temp, q => s_temp, clk => clk, rst => rst);
process(clk, s_temp) is
begin
if rst = '1' then
s <= (others=>'0');
elsif rising_edge(clk) then
s(0) <= so;
end if;
end process;
end Behavioral;```

Answer 1

I think what you are doing is correct, the only thing that you maybe got confused about is the actual shifting itself, you need to shift it the bits by 1 to the left into the other bits. Which can look something like this:
s(7 downto 1) <= s(6 downto 0);
So the final piece of code should look like this: (note that I have removed s_temp from the sensitivity list of the process)
process(clk) is
begin
if rst = '1' then
s <= (others=>'0');
elsif rising_edge(clk) then
s(7 downto 1) <= s(6 downto 0);
s(0) <= so;
end if;
end process;