VHDL Factorial calculator - vhdl

Question

I am attempting to create a 16-bit factorial calculator for an unsigned binary number. In doing so I have created a data path and a state machine that
a.) outputs a final value of 1 if the value input is 0
b.) displays and overflow flag if the input is over 8!
c.) Calculates the value for the factorial if the value input is less then 8 and not zero.
The system seems to fall apart if the value I input is anything over 3 yet still not an overflow. I think the issue is somewhere in Test3, Update 1, update 2 in my state machine. Could anyone help explain what is going wrong?
State Machine:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fact_16_ctrlv2 is
port(
go : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
overflow : in STD_LOGIC;
numeqcnt : in STD_LOGIC;
factzero : in STD_LOGIC;
flag: out STD_logic;
xload : out STD_LOGIC;
cntmux : out STD_LOGIC;
cntload : out STD_LOGIC;
factload : out STD_LOGIC;
factmux : out STD_LOGIC;
finalload : out STD_LOGIC;
finalmuxselect: out STD_logic;
decimalpoint: out std_logic
);
end fact_16_ctrlv2;
--}} End of automatically maintained section
architecture fact_16_ctrlv2 of fact_16_ctrlv2 is
type state_type is (start, input, test1, test2, test3, update1, update2, update3, done);
signal present_state, next_state: state_type;
begin
sreg: process(clk, clr)
begin
if clr='1' then
present_state <= start;
elsif clk'event and clk='1' then
present_state <= next_state;
end if;
end process;
c1: process(present_state, go, overflow, factzero, numeqcnt)
begin
case present_state is
when start =>
if go = '1' then
next_state <= input;
else
next_state <= start;
end if;
when input =>
next_state <= test1;
when test1 =>
if factzero= '1' then
next_state <= done;
else
next_state <= test2;
end if;
when test2 =>
if overflow = '1' then
next_state <= done;
else
next_state <= update3;
end if;
when update3 =>
next_state <= test3;
when test3 =>
if numeqcnt = '1' then
next_state <= done;
else
next_state <= update1;
end if;
when update1 =>
next_state <= update2;
when update2 =>
next_state <= test3;
when done =>
next_state <= done;
when others =>
null;
end case;
end process;
C2: process(present_state, overflow, numeqcnt, factzero)
begin
xload<= '0';
flag <= '0';
cntmux <= '0';
cntload<= '0';
factload<='0';
factmux<='0';
finalload <='0';
finalmuxselect<='0';
decimalpoint<='0';
case present_state is
when input =>
xload<='1';
--cntmux<='1';
--cntload<='1';
when test2 =>
if overflow ='1' then
flag <= '1';
finalmuxselect<='0';
finalload<='1';
factload <='1';
decimalpoint <='1';
end if;
when test1 =>
if factzero ='1' then
flag <= '1';
finalmuxselect <='1';
finalload <='1';
end if;
when update3 =>
cntmux<='1';
cntload<='1';
factmux<= '1';
factload<= '1';
when test3 =>
if numeqcnt ='1' then
finalmuxselect<='0';
--finalload<='1';
factload <='1';
cntload<='1';
factmux<='0';
else
end if;
when update1 =>
factmux<='0';
factload<='1';
when update2 =>
cntmux<='0';
cntload<='1';
--factload<='1';
when done =>
finalload<='1';
when others =>
null;
end case;
end process;
end fact_16_ctrlv2;
Data Path
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fact_16_dp is
port(
clr : in STD_LOGIC;
clk : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(3 downto 0);
overflow : out STD_LOGIC;
finalfact : out STD_LOGIC_VECTOR(15 downto 0);
cntload, cntmult, factload, factmult, xload, finalload :in Std_logic;
equalone, numcnt : out Std_logic;
finalmuxselect, flagin: in STD_logic
);
end fact_16_dp;
--}} End of automatically maintained section
architecture fact_16_dp of fact_16_dp is
-- Component declaration of the "mult16b(mult16b)" unit defined in
-- file: "./../src/multiplier.vhd"
component mult16b
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
p : out STD_LOGIC_VECTOR(15 downto 0));
end component;
for all: mult16b use entity work.mult16b(mult16b);
-- Component declaration of the "comp(comp)" unit defined in
-- file: "./../src/comparitor.vhd"
component comp
generic(
N : INTEGER := 8);
port(
x : in STD_LOGIC_VECTOR(N-1 downto 0);
y : in STD_LOGIC_VECTOR(N-1 downto 0);
gt : out STD_LOGIC;
eq : out STD_LOGIC;
lt : out STD_LOGIC);
end component;
for all: comp use entity work.comp(comp);
-- Component declaration of the "adder(adder)" unit defined in
-- file: "./../src/adder.vhd"
component adder
generic(
N : INTEGER := 8);
port(
a : in STD_LOGIC_VECTOR(N-1 downto 0);
b : in STD_LOGIC_VECTOR(N-1 downto 0);
y : out STD_LOGIC_VECTOR(N-1 downto 0));
end component;
for all: adder use entity work.adder(adder);
-- Component declaration of the "reg(reg)" unit defined in
-- file: "./../src/reg.vhd"
component reg
generic(
N : INTEGER := 8);
port(
load : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(N-1 downto 0);
q : out STD_LOGIC_VECTOR(N-1 downto 0));
end component;
for all: reg use entity work.reg(reg);
-- Component declaration of the "mux2g(mux2g)" unit defined in
-- file: "./../src/mux21.vhd"
component mux2g
generic(
N : INTEGER);
port(
a : in STD_LOGIC_VECTOR(N-1 downto 0);
b : in STD_LOGIC_VECTOR(N-1 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(N-1 downto 0));
end component;
for all: mux2g use entity work.mux2g(mux2g);
-- Component declaration of the "mux4g(mux4g)" unit defined in
-- file: "./../src/mux4to1.vhd"
component mux4g
generic(
N : INTEGER);
port(
a : in STD_LOGIC_VECTOR(N-1 downto 0);
b : in STD_LOGIC_VECTOR(N-1 downto 0);
c : in STD_LOGIC_VECTOR(N-1 downto 0);
s : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC_VECTOR(N-1 downto 0));
end component;
for all: mux4g use entity work.mux4g(mux4g);
--signal cntload, cntmult, numcnt, factload, factmult, xload, numload, equalone, finalload :Std_logic;
signal adderout, cntregout, cntregin, x2 :Std_logic_vector(3 downto 0);
signal xin, factregin, factregout, overin, factmout, checkzero, numregout, flag, finalmuxout, cntregoutb :Std_logic_vector(15 downto 0);
begin
x2 <= x;
xin <= "000000000000" & x2; --Change 4 bit number input into a 16 bit number
cntregoutb <= "000000000000" & cntregout; --change count from 4 bit value to a 16 bit value
flag <= "000000000000000" & flagin;
cntreg : reg --4-bit counter register
generic map(
N => 4
)
port map(
load => cntload,
clk => clk,
clr => clr,
d => cntregin, --not in drawing
q => cntregout
);
factreg : reg --16-bit fact register
generic map(
N => 16
)
port map(
load => factload,
clk => clk,
clr => clr,
d => factregin,
q => factregout
);
--numreg : reg --16-bit num register
--generic map(
--N => 16
--)
--port map(
--load => numload,
--clk => clk,
--clr => clr,
--d => xin,
--q => numregout
--);
xreg : reg --4-bit initial x vlaue register
generic map(
N => 4
)
port map(
load => xload,
clk => clk,
clr => clr,
d => x, --x(3:0)
q => x2
);
finalreg : reg --16-bit final fact register
generic map(
N => 16
)
port map(
load => finalload,
clk => clk,
clr => clr,
d => finalmuxout,
q => finalfact
);
cntmux : mux2g --4-bit cnt mux
generic map(
N => 4
)
port map(
b => "0001", --initial value set
a => adderout, --value after initial run through
s => cntmult,
y => cntregin --cntregin not in drawing
);
factmux : mux2g --16-bit fact mux
generic map(
N => 16
)
port map(
b => "0000000000000001", --initial value set
a => factmout, --value after initial run through
s => factmult,
y => factregin
);
add1 : adder --Increment counter 4-bit
generic map(
N => 4
)
port map(
a => cntregout, --add 1
b => "0001", --1
y => adderout --out of the adder
);
multiplier : mult16b --multiply cnt and fact 16-bit
port map(
a => factregout,
b => cntregoutb, --cnt plus 12 zeros to 16-bit
p => factmout --Multiplier out
);
greater8 : comp --16-bit check x overflow if greater then 8
generic map(
N => 16
)
port map(
x => xin, --check value to 8
y => "0000000000001000",
gt => overflow --send overflow flag
--eq => eq,
--lt => lt
);
check0 : comp --16-bit check x not equal to zero
generic map(
N => 16
)
port map(
x => xin,
y => "0000000000000000",
--gt => gt,
eq => equalone
--lt => lt
);
numeqcnt : comp --16-bit check if num equals cnt
generic map(
N => 16
)
port map(
x => xin,
y => cntregoutb, --need 16 bit
--gt => gt,
eq => numcnt --not in drawing
--lt => lt
);
finalmux: mux2g
generic map(
N => 16
)
port map(
a => factregout,
b => flag,
s => finalmuxselect,
y => finalmuxout
);
end fact_16_dp;
Connected together
-------------------------------------------------------------------------------
--
-- Title : fact_16
-- Design : lab4
-- Author :
-- Company :
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab4\lab4\src\fact_16.vhd
-- Generated : Tue Oct 14 16:40:38 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {fact_16} architecture {fact_16}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fact_16 is
port(
go : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(3 downto 0);
overflowB : out STD_LOGIC;
factout : out STD_LOGIC_VECTOR(15 downto 0)
);
end fact_16;
architecture fact_16 of fact_16 is
-- Component declaration of the "fact_16_dp(fact_16_dp)" unit defined in
-- file: "./../src/fact_16_dp.vhd"
component fact_16_dp
port(
clr : in STD_LOGIC;
clk : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(3 downto 0);
overflow : out STD_LOGIC;
finalfact : out STD_LOGIC_VECTOR(15 downto 0);
cntload : in STD_LOGIC;
cntmult : in STD_LOGIC;
factload : in STD_LOGIC;
factmult : in STD_LOGIC;
xload : in STD_LOGIC;
finalload : in STD_LOGIC;
equalone : out STD_LOGIC;
numcnt : out STD_LOGIC;
finalmuxselect : in STD_LOGIC;
flagin : in STD_LOGIC);
end component;
for all: fact_16_dp use entity work.fact_16_dp(fact_16_dp);
-- Component declaration of the "fact_16_ctrlv2(fact_16_ctrlv2)" unit defined in
-- file: "./../src/fact_16_ctrlv2.vhd"
component fact_16_ctrlv2
port(
go : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
overflow : in STD_LOGIC;
numeqcnt : in STD_LOGIC;
factzero : in STD_LOGIC;
flag : out STD_LOGIC;
xload : out STD_LOGIC;
cntmux : out STD_LOGIC;
cntload : out STD_LOGIC;
factload : out STD_LOGIC;
factmux : out STD_LOGIC;
finalload : out STD_LOGIC;
finalmuxselect : out STD_LOGIC;
decimalpoint : out STD_LOGIC);
end component;
for all: fact_16_ctrlv2 use entity work.fact_16_ctrlv2(fact_16_ctrlv2);
signal overflow, numeqcnt, factzero, xload, cntmux, cntload, factload, flag, factmux, numload, finalload: STD_logic;
signal finalmuxselect: std_logic;
begin
Dpath : fact_16_dp
port map(
clr => clr,
clk => clk,
X => X,
overflow => overflow,
finalfact => factout,
cntload => cntload,
cntmult => cntmux,
factload => factload,
factmult => factmux,
xload => xload,
finalload => finalload,
equalone => factzero,
numcnt => numeqcnt,
finalmuxselect => finalmuxselect,
flagin => flag
);
Cunit : fact_16_ctrlv2
port map(
go => go,
clk => clk,
clr => clr,
overflow => overflow,
numeqcnt => numeqcnt,
factzero => factzero,
flag => flag,
xload => xload,
cntmux => cntmux,
cntload => cntload,
factload => factload,
factmux => factmux,
finalload => finalload,
finalmuxselect => finalmuxselect,
decimalpoint => overflowB
);
end fact_16;