Error loading design while coding a CRC implementation in VHDL - vhdl

Question

While all the code is perfectly compiled by ModelSim, I can't simulate it because of "Error loading design"
This is for a CRC encode and decode using a Linear Feedback Shift Register that uses D-FlipFlop as components. So the project is actually composed by the CRC box that contains the LFSR made by DFF.
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC is
generic (
NBit : positive := 64;
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end CRC;
architecture rtl of CRC is
component LFSR
generic (N : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(N-1 downto 0);
ready :out std_logic
);
end component LFSR;
signal input_temp :std_logic_vector(Nbit-1 downto 0);
signal input_LFSR :std_logic;
signal output_LFSR :std_logic_vector(poly-1 downto 0);
signal ready_LFSR :std_logic;
constant crc_check :std_logic_vector(poly-1 downto 0):= (others => '0');
begin
LFSR_o: LFSR generic map (N => poly)
port map(
clk => clk,
reset => reset,
din => input_LFSR,
dout => output_LFSR,
ready => ready_LFSR
);
process (clk)
variable i : natural := 0;
begin
if (md = '1') then
input_temp(Nbit-1 downto poly)<=input(Nbit-1 downto poly);
input_temp(7 downto 0) <=(others =>'0');
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
dout_s <= input(Nbit-1 downto 0) & output_LFSR;
end if;
end if;
elsif(md = '0') then
input_temp(Nbit-1 downto 0)<=input(Nbit-1 downto 0);
if(rising_edge(clk)) then
input_LFSR <= input_temp(i);
i:= i+1;
if(ready_LFSR = '1') then
--codice per il controllo
for t in 0 to poly-1 loop
if (output_LFSR(t)='1') then
dout_r <=(others =>'0');
exit;
elsif(t=poly-1 and output_LFSR(t)='0') then
dout_r <= input(Nbit-1 downto poly);
end if;
end loop;
end if;
end if;
end if;
end process;
end rtl;
here the LFSR
library IEEE;
use IEEE.std_logic_1164.all;
entity LFSR is
generic (NBit : positive := 8);
port(
clk :in std_logic;
reset :in std_logic;
din :in std_logic;
dout :out std_logic_vector(Nbit-1 downto 0);
ready :out std_logic
);
end LFSR;
architecture rtl of LFSR is
component DFC
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end component DFC;
signal q_s : std_logic_vector (NBit-1 downto 0):= (others => '0');
signal crc_t : std_logic_vector (NBit-1 downto 0):= (others => '0'); --registro temporaneo su cui fare le operazioni
signal int_0 :std_logic := '0';
signal int_2 :std_logic := '0';
signal int_4 :std_logic := '0';
signal int_8 :std_logic := '0';
begin
int_0<= din xor q_s(7);
int_2<= q_s(1) xor q_s(7);
int_4<= q_s(3) xor q_s(7);
GEN: for i in 0 to Nbit-1 generate
FIRST: if i=0 generate
FF1: DFC port map (
clk => clk,
reset => reset,
d => int_0,
crc => crc_t(i), --funziona benissimo se metto dout(i)
q => q_s(i)
);
end generate FIRST;
THIRD: if i=2 generate
FF2: DFC port map (
clk => clk,
reset => reset,
d => int_2,
crc => crc_t(i),
q => q_s(i)
);
end generate THIRD;
FIFTH: if i=4 generate
FF4: DFC port map (
clk => clk,
reset => reset,
d => int_4,
crc => crc_t(i),
q => q_s(i)
);
end generate FIFTH;
INTERNAL: if i>0 and i<Nbit-1 and i/= 2 and i/=4 generate
FFI: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate INTERNAL;
LAST: if i=Nbit-1 generate
FFN: DFC port map (
clk => clk,
reset => reset,
d => q_s(i-1),
crc => crc_t(i),
q => q_s(i)
);
end generate LAST;
end generate GEN;
process(clk)
variable t : natural := 0;
begin
--ready <= '0';
if(rising_edge(clk)) then
t:= t+1;
if t=24 then --per qualche ragione ho bisogno di 3 cicli di clock in più per arrivare al risultato ricercato
dout <= crc_t;
ready <='1';
end if;
end if;
end process;
end rtl;
here the DFF
library IEEE;
use IEEE.std_logic_1164.all;
entity DFC is
port(
clk :in std_logic;
reset :in std_logic;
d :in std_logic;
crc :out std_logic;
q :out std_logic
);
end DFC;
architecture rtl of DFC is
begin
process(clk, reset, d)
begin
if(reset = '1')then
q <= '0';
crc<= '0';
elsif (clk'event and clk='1') then
q <= d;
crc <= d;
end if;
end process;
end rtl;
and finally here the testbench for the CRC
library IEEE;
use IEEE.std_logic_1164.all;
entity CRC_tb is
end CRC_tb;
architecture testbench of CRC_tb is
component CRC is
generic (
NBit : positive := 20; --da rimettere a 64
poly : positive := 8
);
port(
clk :in std_logic;
reset :in std_logic;
md :in std_logic; --1 per sender, 0 per receiver
input :in std_logic_vector(Nbit-1 downto 0);
dout_s :out std_logic_vector(Nbit-1 downto 0);
dout_r :out std_logic_vector(Nbit-poly-1 downto 0)
);
end component;
constant T_CLK :time := 25 ns;
constant T_sim :time := 2000 ns;
signal sim_time :std_logic :='1';
constant M :integer :=20; --da rimettere a 64, Nbit
constant N :integer :=8; -- poly
signal clk_tb :std_logic :='0';
signal reset_tb :std_logic :='1';
signal md_tb :std_logic;
signal input_tb :std_logic_vector(M-1 downto 0);
signal dout_s_tb :std_logic_vector(M-1 downto 0);
signal dout_r_tb :std_logic_vector(M-N-1 downto 0);
begin
clk_tb <= (not(clk_tb)and sim_time) after T_CLK/2;
sim_time <= '0' after T_sim;
DUT_i : CRC
generic map (
Nbit => M,
poly => N
)
port map (
clk => clk_tb,
reset => reset_tb,
md => md_tb,
input => input_tb,
dout_s => dout_s_tb,
dout_r => dout_r_tb
);
input_process : process(clk_tb)
begin
if(rising_edge(clk_tb)) then
md_tb <= '1';
input_tb <= "10100111010000000000";
end if;
end process input_process;
end testbench;
I was expecting that everything went fine given that the CRC code doesn't do much if not creating connections. I'm very new to VHDL so I can't understand very well what
** Error: (vsim-3733) C:/Modeltech_pe_edu_10.4a/CRC2.0/CRC.vhd(50):
No default binding for component instance 'LFSR_o'.
The following component generic is not on the entity: N Time: 0 ns
Iteration: 0 Instance: /crc_tb/DUT_i/LFSR_o File:
C:/Modeltech_pe_edu_10.4a/CRC2.0/LFSR.vhd
Loading work.dfc(rtl)
Error loading design
means.
Thanks all for the answers.