(VHDL) Two components in top level entity but only one working - vhdl

Question

I am programming in VHDL 1993 under QUARTUS II, and I just created two components in order to try solve the problem I am about to present as they weren't the solution. Before hand, the components files are included in the design and working one at a time.
So in my basic application I am trying to do two jobs, one is to blink a led and to turn on another led controlled by a switch, when I declare both components only the one controlling the led with the switch works, then when I undeclared the led-switch component and it's signals IN THE TOP LEVEL ENTITY the blinker works, I am guessing then it's a problem with the signal declarations at the top level entity "test2", but I don't understand why it works only when using one thing at a time, what I coded at the top level entity is:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test2 is
port( clk_cpu, K2: in std_logic;
led1, led2: out std_logic);
end test2;
architecture struct of test2 is
component tmp_toogler
port( clk: in std_logic;
led: out std_logic);
end component;
component yes_driver
port( input: in std_logic;
output: out std_logic);
end component;
begin
instanciaD: yes_driver PORT MAP(
K2, led2
);
instancia1: tmp_toogler PORT MAP(
clk_cpu, led1
);
end struct;
The blinker component:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tmp_toogler is
port( clk: in std_logic;
led: out std_logic);
end tmp_toogler;
architecture struct of tmp_toogler is
signal counter: integer range 0 to 50000000;
signal state : std_logic := '1';
begin
process(clk)
begin
if(rising_edge(clk)) then
counter <= counter + 1;
end if;
if(counter = 50000000) then
counter <= 0;
if(state = '0') then
led <= '1';
state <= '1';
else
led <= '0';
state <= '0';
end if;
end if;
end process;
end struct;
The led-switch:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity yes_driver is
port( input: in std_logic;
output: out std_logic);
end yes_driver;
architecture struct of yes_driver is
begin
process(input)
begin
output <= input;
end process;
end struct;
I feel this is a very basic question about doing multiple tasks, so I am urging for some help, thanks in advance.