I want to make a D ff with a little delay on the reset, D will always be '1', clk will be controlled by a switch(it will give a command for a specific floor on an elevator) and count_aux will be a 1Hz clock, but when I try to synthesize it shows me this error "ERROR:Xst:1534 - Sequential logic for node appears to be controlled by multiple clocks.". I don't want to clk to be understood as a clock, since it will be just a switch. How can I do that?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_FF is
port ( D: in std_logic;
clk: in std_logic;
count_aux: in std_logic;
reset: in std_logic;
Q: out std_logic:='0'
);
end D_FF;
architecture a1 of D_FF is
signal i: std_logic_vector(3 downto 0):="0000";
begin
proc: process (D,clk,reset)
begin
if (reset='1') then
if(count_aux'event and count_aux='1') then i<=i+1;
if (i="0001") then
q<='0';
i<="0000";
end if;
end if;
elsif (clk'event and clk='1') then
q<=d;
end if;
end process proc;
end a1;
You are using clk as a clock in the process, so it will be a clock ;) But the weird thing for the synthesis is that you want to have a clocked flipflop (sequential element or regeister or what ever) but yet you also include combinatorial logic into the reset. So it has no idea what to synthesize since it has no component in the library for this logic.
So my advise is to keep the sequential and combinatorial logic separate. Sequential logic will have only clk and reset in the sensitivity list and have the code structure of:
process(clk, reset)
begin
if reset = 1 then
foobar <= '0';
elsif rising_edge(clk) then
foobar <= foo + bar;
end if;
end process;
Related
There is something I do not understand about VHDL processes ending with an unconditional wait statement. To illustrate my problem, I need to compare the 2 following snipets :
snipet 1 :
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture sim of foo is
signal clk : std_logic := '0';
signal s : std_logic;
begin
clk <= not clk after 10 ns;
-- driver1
s <= '0';
-- driver2
process (clk) is
begin
s <= clk;
end process;
end architecture;
There is a double assignment for signal s: Driver1 drives the signal s to '0' while driver2 alternatively drives it to '0' and '1'. As we can see on the waveform graph, when clk is '0', the resulting s is '0' (green segments) but when clk is '1', the resulting s is 'X' (red segments).
=> I understand this behaviour, no problem with that one.
If I modify slightly this code by changing driver1 into a process ended with an unconditional wait instruction :
snipet2 :
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture sim of foo is
signal clk : std_logic := '0';
signal s : std_logic;
begin
clk <= not clk after 10 ns;
-- driver1
-- s <= '0';
process
begin
s <= '0';
wait;
end process;
-- driver2
process (clk) is
begin
s <= clk;
end process;
end architecture;
Surprisingly, for me, the snipet 2 produces the same waveform as the snipet 1. My understanding is that the instructions inside a process with a final "unconditional" wait statement will stop forever, meaning that their code will be inactive after the first execution run. But if this is truly the case, I would expect that driver1 in snipet 2 is inactive after its first run, and that from that point driver2 remains the only active driver of signal s, always assigning clk's alternative '1's and '0's to it.
Why isn't it the case?
When you assign a signal in a process, a driver is created for that signal from the moment it assigned until the end of simulation. So here, both code snippets are functionally equivalent, you create driver1 from time 0 and driver2 from the first clock.
I am new to VHDL and I can't see a solution to my problem. I want to find a VHDL code for my 3-bit sequence counter with T Flip Flop's which goes: ..,0,4,5,7,6,2,3,1,0,... I made a truth table and minimized equations for T_FF like so:
T0=Q2 xor Q1 xor Q0;
T1=(Q2 xor Q1) and Q0;
T2= not(Q2 xor Q1) and Q0;
Then I draw the circuit:
Last VHDL:
T-FLIP FLOP
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port(
clk: in std_logic;
reset: in std_logic;
t: in std_logic;
q: out std_logic
);
end tff;
architecture behave of tff is
-- signal q_reg: std_logic; --v registru
-- signal q_next: std_logic; --naslednje stanje
begin
process
variable x: std_logic:='0';
begin
wait on clk;
if (clk' event and clk = '1') then
if reset='1' then
x:='0';
else x:=t;
end if;
end if;
if (t = '1') then
q<=not x;
else
q<=x;
end if;
end process;
end behave;
-----------------------------------------------------------
Gray counter
library ieee;
use ieee.std_logic_1164.all;
entity tff_gray is
port(
clk: in std_logic;
reset: in std_logic;
q: inout std_logic_vector (2 downto 0)
--q: out std_logic
);
end tff_gray;
architecture behave of tff_gray is
component tff is
port(
clk: in std_logic;
reset: in std_logic;
t: in std_logic;
q: out std_logic
);
end component;
signal i0,i1,i2: std_logic; --v registru
--signal q_next: std_logic; --naslednje stanje
begin
i0<=q(0) xor q(1) xor q(2);
i1<=q(0) and (q(1) xor q(2));
i2<=q(0) and not(q(1) xor q(2));
Tff0: tff port map(clk, reset, i0, Q(0));
Tff1: tff port map(clk, reset, i1, Q(1));
Tff2: tff port map(clk, reset, i2, Q(2));
end behave;
I wrote this bunch of code of what I found over the internet. When I compiled my code it all went through without a problem but the simulation is wrong. I went through this code a lot of times and I don't know what is wrong. If anyone has any idea please share.
I have mostly watched this altera site and LBEbooks on YouTube.
A number of things. Firstly:
T-FF aka toggle flip flop
You've got your toggle flip-flop description incorrect.
A toggle flip flop flips the output if T='1'. so:
signal q_int : std_logic := '0';
begin
tff_proc: process(clk) begin
if rising_edge(clk) then
if t='1' then
q_int <= not q_int;
end if;
-- reset statement
if reset='1' then
q_int <= '0';
end if;
end if;
end process;
q <= q_int;
redundant code
Don't combine wait on clk and if (clk'event and clk='1') as they do the same thing. Combining will cause issues. Refer to my example above for correct instantiations.
component instantiation
You don't need to include the component tff code in your tff_gray entity. Just simply instantiate the entity directly from the library. e.g.
Tff0: entity work.tff port map(clk, reset, i0, q(0));
bidirectional ports (inout type)
Using the inout type, which you use for the q of tff_gray can give problems in simulation and implementation. It should be out.
However, you must have encountered the cannot read outputs error. This is no longer an issue in VHDL-2008, so you should compile using VHDL-2008 mode.
Alternatively, you need to use intermediate signals, like I did in the example above. E.g.
signal q_int : std_logic_vector(2 downto 0) := (others => '0');
[...]
q <= q_int;
I tried to create a flip-flop which has a reset-enable and a synchronous data load. It works fine in VHDL simulation, but when I try to synthesize it in ISE it gives me the following error:
Line 24: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition
Here is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_FF is
port (D: in std_logic;
clk: in std_logic;
reset_enable: in std_logic;
reset: in std_logic;
Q: out std_logic:='0'
);
end D_FF;
architecture a1 of D_FF is
begin
proc: process (D,clk,reset,reset_enable)
begin
if (reset_enable='1') then
if (reset='1') then
q<='0';
end if;
end if;
if (clk'event and clk='1') then -- Line 24
q<=d;
end if;
end process proc;
end a1;
How can I fix this error in order to make the code synthesizable and also equivalent to the one I wrote?
To point you into the right direction: What happens when there is a reset AND a clk edge at the same time?
A solution:
if (reset = '1' and reset_enable = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
q <= d;
end if;
I have been going crazy trying to make it work but nothing been on this for the past 6 hours and still didn't solve it :/
so this the top module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test is
Port ( CLKI : in STD_LOGIC;
HSO : out STD_LOGIC;
VSO : out STD_LOGIC;
RO,GO,BO : out STD_LOGIC);
end Test;
architecture Behavioral of Test is
component CLK_25Mhz_Divider
Port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end component;
component VGA_Sync
Port ( CLK : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
R,G,B : out STD_LOGIC);
end component;
signal CLKBE: STD_LOGIC;
begin
CLK_Divider_1: CLK_25Mhz_Divider port map ( CLK => CLKI,
CLK_OUT => CLKBE);
VGA_S1: VGA_Sync port map ( CLK => CLKBE,
HS => HSO,
VS => VSO,
R => RO,
G => GO,
B => BO );
end Behavioral;
the clock divider
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLK_25MHz_Divider is
Port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end CLK_25MHz_Divider;
architecture Behavioral of CLK_25MHz_Divider is
BEGIN
PROCESS(CLK)
VARIABLE COUNT : INTEGER:=0;
VARIABLE TEMP : STD_LOGIC:='0';
BEGIN
IF RISING_EDGE(CLK)THEN
COUNT:=COUNT+1;
IF COUNT=2 THEN
TEMP:=NOT TEMP;
COUNT:=0;
END IF;
END IF;
CLK_OUT<=TEMP;
END PROCESS;
end Behavioral;
The VGA signal generation module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_Sync is
Port ( CLK : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
R,G,B : out STD_LOGIC);
end VGA_Sync;
architecture Behavioral of VGA_Sync is
begin
process(CLK)
Variable countH : Integer := 0;
Variable countV : Integer := 0;
begin
if (CLK'EVENT and CLK = '1') then
if countH < 800 then
countH := countH + 1;
else
countH := 0;
if countV < 500 then
countV := countV + 1;
else
countV := 0;
end if;
end if;
if countH >= 16 and countH < 112 then
HS <= '0';
else
HS <= '1';
end if;
if countV >= 10 and countV < 12 then
VS <= '0';
else
VS <= '1';
end if;
if (countH < 160) or (countV < 45) then
R <= '0';
G <= '0';
B <= '0';
else
R <= '1';
G <= '0';
B <= '1';
end if;
end if;
end process;
end Behavioral;
so tell me your thoughts on what is wrong with the code
Because you haven't actually describe the problem and because I had a testbench for a 25 MHz clocked vga generator that only required changing the type for r, g and b, I ran you sync_vga against the testbench:
library ieee;
use ieee.std_logic_1164.all;
entity vga_sync_tb is
end entity;
architecture foo of vga_sync_tb is
signal clk: std_logic := '0';
signal hs: std_logic;
signal vs: std_logic;
signal r,g,b: std_logic;
begin
DUT:
entity work.vga_sync
port map (
clk => clk,
hs => hs,
vs => vs,
r => r,
g => g,
b => b
);
CLOCK:
process
begin
wait for 20 ns; -- clock period 25 MHz = 40 ns;
clk <= not clk;
if now > 20 ms then -- one frame time plus a bit
wait;
end if;
end process;
end architecture;
It gave a vertical sync rate around 60 Hz:
Zooming in and measuring between two HS edges shows a horizontal rate of around 31.17 KHz.
You have horizontal and vertical blanking intervals and your R, G, and B does what your code says.
That sort of leaves the clock divider or something platform related.
Because a testbench for the clock is simple:
library ieee;
use ieee.std_logic_1164.all;
entity clock_tb is
end entity;
architecture foo of clock_tb is
signal clk: std_logic := '0';
signal clk25: std_logic;
begin
DUT:
entity work.clk_25mhz_divider
port map (
clk => clk,
clk_out => clk25
);
CLOCK:
process
begin
wait for 10 ns; -- half the period of 50 MHz
clk <= not clk;
if now > 130 ns then
wait;
end if;
end process;
end architecture;
It demonstrates Martin Zabel's answer:
That your divide by two actually divides by four. giving a period of 80 ns (12.5 MHz).
This demonstrates the usefulness of simulation and in simulation it can also be helpful to use signals instead of variables which have no history. Variables don't have a projected output waveform and he simulator has to attach extra code to display them in a waveform.
The simulation performance increase using variables instead of signals is traded for the ability to display them and there is no interesting distinction in synthesis.
From comments below question:
at that resolution i should use 25Mhz so i using the onboard clock
that's 50 Mhz and dividing it using the Clock divider module. –
Mostafa
Your clock divider divides the input frequency by 4 instead of 2. You toggle TEMP every two cycles of CLK which is CLKI of the top module. So a full cycle of CLK_OUT takes 4 cycles of the input clock.
To divide by two, you must toggle TEMP every clock cycle of the input clock:
architecture Behavioral of CLK_25MHz_Divider is
BEGIN
PROCESS(CLK)
VARIABLE TEMP : STD_LOGIC:='0';
BEGIN
IF RISING_EDGE(CLK)THEN
TEMP:=NOT TEMP;
END IF;
CLK_OUT<=TEMP;
END PROCESS;
end Behavioral;
Starting with TEMP = '0', it toggles to '1' at the first rising edge of CLK. At the second rising edge, TEMP toggles to '0', and at the third rising edge back to '1'. The duration between the first and third rising-edge of the 50 MHz input clock is 40 ns, which makes a frequency of 25 MHz for the output clock.
I am using modelsim for simulating a pseudo-random pattern generator using the below code. The problem is when i force the data_reg signal to a seed value (ex: 0001010101101111) the data_out shows the same value instead of a random value. i will really appreciate any help i cud get on this one.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
VHDL CODE FOR PRBS Generator using LFSR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lfsr is
Port ( CLK : in STD_LOGIC;
RSTn : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end lfsr;
architecture Behavioral of lfsr is
component dff
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
signal data_reg : std_logic_vector(15 downto 0);
signal tap_data : std_logic;
begin
process(CLK)
begin
tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor
data_reg(15));
end process;
stage0: dff
port map(CLK, RSTn, tap_data, data_reg(0));
g0:for i in 0 to 14 generate
stageN: dff
port map(CLK, RSTn, data_reg(i), data_reg(i+1));
end generate;
data_out <= data_reg after 3 ns;
end Behavioral;
First off. In your LFSR you have a process sensitive to CLK which should only be combinational:
process(CLK) -- Not correct
-- Change to the following (or "all" in VHDL-2008)
process(data_reg)
You could also just implement it as a continuous assignment outside of a formal process which is functionally the same in this case.
When you force data_reg to a value you are overriding the normal signal drivers instantiated in the design. In the GUI the force command defaults to "Freeze". Once that is in place, the drivers can't update data_reg because the freeze force is dominant until you cancel it. In the force dialog select the "Deposit" kind to change the state without overriding the drivers on subsequent clocks.
The Modelsim documentation has this to say about the different force kinds:
freeze -- Freezes the item at the specified value until it is forced again or until it is unforced with a noforce command.
drive -- Attaches a driver to the item and drives the specified value until the item is forced again or until it is unforced with a noforce command. This option is illegal for unresolved signals.
deposit -- Sets the item to the specified value. The value remains until there is a subsequent driver transaction, or until the item is forced again, or until it is unforced with a noforce command
Note: While a lot of instructional materials (unfortunately) demonstrate the use of the std_logic_arith and std_logic_unsigned libraries, these are not actual IEEE standards and shouldn't be used in standard conformant VHDL. Use numeric_std instead or, in your case, just eliminate them since you aren't using any arithmetic from those libraries.