Structural Architucture Simulation in ACtive-HDL - vhdl

Question

I have written two codes that successfully simulated in ISE Design Suit:
-- 2X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux2to1_pkg is
component mux2to1
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end component;
end mux2to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
f <= (d0 and not s) or
(d1 and s);
end behavioral;
and
-- 6X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux6to1_pkg is
component mux6to1
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end component;
end mux6to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.mux2to1_pkg.all;
entity mux6to1 is
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
signal m1,m2,m3,m4: std_logic;
begin
mux1: mux2to1 port map(d(5),d(4),s(0),m1);
mux2: mux2to1 port map(d(3),d(2),s(0),m2);
mux3: mux2to1 port map(d(1),d(0),s(0),m3);
mux4: mux2to1 port map(m2,m3,s(1),m4);
mux5: mux2to1 port map(m1,m4,s(2),f);
end structural;
The problem is when I want to simulate the MUX6to1 in Active-HDL the output doesn't change at all. What's the secret in this program? Ty.

Answer 1

Using this test bench:
library ieee;
use ieee.std_logic_1164.all;
entity mdl_tb is
end entity;
library ieee;
use ieee.numeric_std.all;
architecture sim of mdl_tb is
signal s_d : std_logic_vector(8 downto 0) := (others => '0');
signal f : std_logic;
begin
dut_e : entity work.mux6to1
port map(d => s_d(5 downto 0),
s => s_d(8 downto 6),
f => f);
process is
begin
wait for 1 ns;
s_d <= std_logic_vector(unsigned(s_d) + 1);
end process;
end architecture;
it shows changes like:
based on this Active-HDL script with the above two files in mdl.vhd:
# Workspace "prod" create under current and open this workspace
workspace create prod
# Design "prod" create under current workspace
design create -a prod .
# Create to directory under workspace
cd $DSN/..
# Compile
acom ../mdl.vhd
acom ../mdl_tb.vhd
# Load module for simulation
asim work.mdl_tb
# Waveform add
add wave /mdl_tb/*
# Run
run 600 ns
Btw. you can reduce the code significantly if you skip the component declarations and related packages, through code like:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
f <= d0 when (s = '0') else d1;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux6to1 is
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
signal m1,m2,m3,m4: std_logic;
begin
mux1: entity work.mux2to1 port map(d(5),d(4),s(0),m1);
mux2: entity work.mux2to1 port map(d(3),d(2),s(0),m2);
mux3: entity work.mux2to1 port map(d(1),d(0),s(0),m3);
mux4: entity work.mux2to1 port map(m2,m3,s(1),m4);
mux5: entity work.mux2to1 port map(m1,m4,s(2),f);
end structural;