For the following VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(
d, clk: in std_logic;
q: out std_logic);
end dff;
architecture behave of dff is
begin
process(clk)
begin
if(clk = '1') then
q<= d;
end if;
end process;
end behave;
---------------------------------------------------------------------
and and a testbench:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
end dff;
architecture behave of dff is
component dff is
port(d, clk: in std_logic;
q: out std_logic);
end component;
signal d_in: std_logic;
signal clk_in: std_logic;
signal q_out: std_logic;
begin
d_ff : dff port map( d_in, clk_in, q_out);
process
begin
if(clk_in = '1') then
q_out<= d_in;
end if;
end process;
end behave;
When trying to simulate Modelsim is showing the following error:
#Error loading design
The following component ports are not on the entity:
q
clk
d
The entity name of your testbench is also dff. You need to give it a different name (eg dff_tb). So, when you compile your testbench, it is overwriting the other dff entity.
Related
I made a state automate for this diagram:
Diagram with states
(not a from diagram represents a='0' and b with horizontal bar above represents b='0')
And I write structural and comportamental automate, structural with mux4:1 and 3 d flip-flops.
I made a testbench file in which i give simulate values for a and b variables like this:
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
b<='1' after 11ns,'0' after 13ns;
, for clock:
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
and for an asynchronous reset:
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
with this rn i will be starting showing the states and giving a logic value for a and b only after 2 ns
Test result is wrong
The test shows the wrong states for structural description only for first scrolling, after that is equal to the comportamental description. How I can make to show all the curls for this diagram, not only this which is the complete?
I add there the vhdl code for structural and comportamental description, mux4, d flip-flop and test:
Structural:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end automat;
architecture structural of automat is
component mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end component;
signal q2,q1,q0,d2,d1,d0:std_logic;
signal an,bn,q0n:std_logic;
signal net1,net2:std_logic;
begin
q0n<=not q0;
q<=q2& q1& q0;
an<=not a;
bn<=not b;
--cele 5 muxuri necesare descrierii structurale
mux412:mux4 port map(i0=>'1',i1=>'0',i2=>'0',i3=>'0',a1=>q0,a0=>b,y=>net1);
mux41:mux4 port map(i0=>'0',i1=>a,i2=>'1',i3=>net1,a1=>q2,a0=>q1,y=>d2);
mux42:mux4 port map(i0=>'1',i1=>an,i2=>q0,i3=>q0n,a1=>q2,a0=>q1,y=>d1);
mux432: mux4 port map(i0=>'0',i1=>'1',i2=>'0',i3=>'0',a1=>q0,a0=>a,y=>net2);
mux43:mux4 port map(i0=>'1',i1=>an,i2=>net2,i3=>q0n,a1=>q2,a0=>q1,y=>d0);
--cele 3 bistabile d necesare
dff2:dff port map(d=>d2, ck=>ck, rn=>rn, q=>q2);
dff1:dff port map(d=>d1, ck=>ck, rn=>rn, q=>q1);
dff0:dff port map(d=>d0, ck=>ck, rn=>rn, q=>q0);
end architecture;
Mux4:1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere multiplexor 4:1
entity mux4 is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3: in STD_LOGIC;
Y : out STD_LOGIC);
end mux4;
architecture Behavioral of mux4 is
signal A : STD_LOGIC_VECTOR(1 downto 0);
begin
--mux4: process (a1,a0,i0,i1,i2,i3)
--begin
A<=a1 & a0;
Y<=i0 when A="00"
else i1 when A="01"
else i2 when A="10"
else i3;
end Behavioral;
D Flip-Flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--descriere bistabil d
entity dff is
Port ( d : in STD_LOGIC;
ck : in STD_LOGIC;
rn: in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
flip_flop: process(ck,rn)
begin
if rn='0' then
q <= '0';
else
if rising_edge(ck) then
q <= d;
qn <= not d;
end if;
end if;
end process;
end Behavioral;
Comportamental:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end combinat;
architecture Behavioral of combinat is
signal cur_poz,next_poz:std_logic_vector(2 downto 0);
begin
q<=cur_poz;
process(ck,rn)
begin
if rn='0' then
cur_poz<="000";
elsif rising_edge(ck) then
cur_poz<=next_poz;
end if;
end process;
process(cur_poz,a,b)
begin
case cur_poz is
when "000"=>next_poz<="011";
when "011"=>if a='1' then
next_poz<="100";
else
next_poz<="011";
end if;
when "100"=>if a='1' then
next_poz<="101";
else
next_poz<="100";
end if;
when "101"=>next_poz<="110";
when "110"=>if b='1' then
next_poz<="011";
else
next_poz<="111";
end if;
when "111"=>next_poz<="000";
when others=>next_poz<="000";
end case;
end process;
end Behavioral;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
-- Port ( );
end test;
architecture Behavioral of test is
component automat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
component combinat is
Port ( ck : in STD_LOGIC;
rn : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end component;
signal ck,rn,a,b:std_logic;
signal qsec,qcomb:std_logic_vector(2 downto 0);
begin
Testare1: automat port map(ck=>ck,--pentru test descriere structurala
rn=>rn,
a=>a,
b=>b,
q=>qsec);
Testare2:combinat port map(ck=>ck,--pentru test descriere comportamentala
rn=>rn,
a=>a,
b=>b,
q=>qcomb);
rn<='1' after 0ns,'0' after 0.2ns,'1' after 2ns;
process
begin
ck<='0';
wait for 0.5ns;
ck<='1';
wait for 0.5ns;
end process;
a<='0' after 2ns,'1' after 5ns,'0' after 8ns,'1' after 11ns,'1' after 16ns;--se va incepe dupa rn, dupa 2 ns
--evaluarea timpilori si valorilor parametrilor conform buclelor din diagrama gasite
b<='1' after 11ns,'0' after 13ns;
--a<='0' after 2ns,'1' after 4ns,'0' after 6ns,'1' after 8ns,'0' after 16ns;
--b<='1' after 8ns,'0' after 10ns;
verificare:process(qsec)--verificare daca corespund rezultatele celor 2 structuri
begin
if qsec/=qcomb then
report "Rezultat al descrierii structurale diferit fata de cea comportamentale";
end if;
end process;
end Behavioral;
I am programming in VHDL 1993 under QUARTUS II, and I just created two components in order to try solve the problem I am about to present as they weren't the solution. Before hand, the components files are included in the design and working one at a time.
So in my basic application I am trying to do two jobs, one is to blink a led and to turn on another led controlled by a switch, when I declare both components only the one controlling the led with the switch works, then when I undeclared the led-switch component and it's signals IN THE TOP LEVEL ENTITY the blinker works, I am guessing then it's a problem with the signal declarations at the top level entity "test2", but I don't understand why it works only when using one thing at a time, what I coded at the top level entity is:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test2 is
port( clk_cpu, K2: in std_logic;
led1, led2: out std_logic);
end test2;
architecture struct of test2 is
component tmp_toogler
port( clk: in std_logic;
led: out std_logic);
end component;
component yes_driver
port( input: in std_logic;
output: out std_logic);
end component;
begin
instanciaD: yes_driver PORT MAP(
K2, led2
);
instancia1: tmp_toogler PORT MAP(
clk_cpu, led1
);
end struct;
The blinker component:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tmp_toogler is
port( clk: in std_logic;
led: out std_logic);
end tmp_toogler;
architecture struct of tmp_toogler is
signal counter: integer range 0 to 50000000;
signal state : std_logic := '1';
begin
process(clk)
begin
if(rising_edge(clk)) then
counter <= counter + 1;
end if;
if(counter = 50000000) then
counter <= 0;
if(state = '0') then
led <= '1';
state <= '1';
else
led <= '0';
state <= '0';
end if;
end if;
end process;
end struct;
The led-switch:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity yes_driver is
port( input: in std_logic;
output: out std_logic);
end yes_driver;
architecture struct of yes_driver is
begin
process(input)
begin
output <= input;
end process;
end struct;
I feel this is a very basic question about doing multiple tasks, so I am urging for some help, thanks in advance.
I am getting this error while trying to implement a D flip-flop and simulate it:
VRFC 10-718] formal port does not exist in entity .
Please compare the definition of block to its component
declaration and its instantiation to detect the mismatch.
I am new to the language and can't figure out why this happening.
Bellow is my VHDL code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Interfata is
port(
clk : in std_logic;
data :in std_logic;
Q : out std_logic;
Qnot : out std_logic
);
end Interfata;
architecture Behavioral of Interfata is
component LATCH
port(
set : in std_logic;
reset : in std_logic;
data : out std_logic;
data_not : out std_logic
);
end component;
signal latch_set: std_logic;
signal latch_reset:std_logic;
begin
uut1: latch port map(
set => latch_set,
reset => latch_reset,
data => Q,
data_not => Qnot
);
process(clk,data)
begin
if(clk' event and clk='1') then
latch_set <= data;
latch_reset <= not data;
end if;
end process;
end Behavioral;
here's the latch.vhd code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity latch is
port(
set : in std_logic;
reset :in std_logic;
data : out std_logic;
data_not : out std_logic
);
end latch;
architecture Behavioral of latch is
signal data_temp : std_logic:='0';
signal data_not_temp : std_logic:='1';
begin
process(set, reset) begin
data_temp <= not(reset or data_not_temp);
data_not_temp <= not(set or data_temp);
data <= data_temp;
data_not <= data_not_temp;
end process;
end Behavioral;
I have written two codes that successfully simulated in ISE Design Suit:
-- 2X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux2to1_pkg is
component mux2to1
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end component;
end mux2to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
f <= (d0 and not s) or
(d1 and s);
end behavioral;
and
-- 6X1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux6to1_pkg is
component mux6to1
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end component;
end mux6to1_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.mux2to1_pkg.all;
entity mux6to1 is
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
signal m1,m2,m3,m4: std_logic;
begin
mux1: mux2to1 port map(d(5),d(4),s(0),m1);
mux2: mux2to1 port map(d(3),d(2),s(0),m2);
mux3: mux2to1 port map(d(1),d(0),s(0),m3);
mux4: mux2to1 port map(m2,m3,s(1),m4);
mux5: mux2to1 port map(m1,m4,s(2),f);
end structural;
The problem is when I want to simulate the MUX6to1 in Active-HDL the output doesn't change at all. What's the secret in this program? Ty.
Using this test bench:
library ieee;
use ieee.std_logic_1164.all;
entity mdl_tb is
end entity;
library ieee;
use ieee.numeric_std.all;
architecture sim of mdl_tb is
signal s_d : std_logic_vector(8 downto 0) := (others => '0');
signal f : std_logic;
begin
dut_e : entity work.mux6to1
port map(d => s_d(5 downto 0),
s => s_d(8 downto 6),
f => f);
process is
begin
wait for 1 ns;
s_d <= std_logic_vector(unsigned(s_d) + 1);
end process;
end architecture;
it shows changes like:
based on this Active-HDL script with the above two files in mdl.vhd:
# Workspace "prod" create under current and open this workspace
workspace create prod
# Design "prod" create under current workspace
design create -a prod .
# Create to directory under workspace
cd $DSN/..
# Compile
acom ../mdl.vhd
acom ../mdl_tb.vhd
# Load module for simulation
asim work.mdl_tb
# Waveform add
add wave /mdl_tb/*
# Run
run 600 ns
Btw. you can reduce the code significantly if you skip the component declarations and related packages, through code like:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2to1 is
port(d1,d0: in std_logic;
s: in std_logic;
f: out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
f <= d0 when (s = '0') else d1;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux6to1 is
port(d: in std_logic_vector(5 downto 0);
s: in std_logic_vector(2 downto 0);
f: out std_logic);
end mux6to1;
architecture structural of mux6to1 is
signal m1,m2,m3,m4: std_logic;
begin
mux1: entity work.mux2to1 port map(d(5),d(4),s(0),m1);
mux2: entity work.mux2to1 port map(d(3),d(2),s(0),m2);
mux3: entity work.mux2to1 port map(d(1),d(0),s(0),m3);
mux4: entity work.mux2to1 port map(m2,m3,s(1),m4);
mux5: entity work.mux2to1 port map(m1,m4,s(2),f);
end structural;
I am new to VHDL. I have this entity (shortened):
entity foo is
port (CLK : in std_logic;
out_A : out std_logic;
);
end foo;
architecture Structure of foo is
component D_Flipflop
port (
D : in std_logic;
CLK : in std_logic;
Q : out std_logic;
not_Q : out std_logic);
end component;
signal D_A, qA, not_qA : std_logic;
begin
my_Flipflop : D_Flipflop
port map(
not_qA,
CLK,
qA,
not_qA
);
end Structure;
As you can see, I want to use the D_Flipflop like a Toggle-Flipflop, so I redirected the output to the input by the signal not_qA (is that possible?). The problem is that from outside, only the port CLK of foo is visible as input and - at least in the Vivado Simulator - the signals qA and not_qA are never evaluated.
This is the architecture of D_Flipflop:
architecture Behavioral of D_Flipflop is
begin
set_state : process(CLK, D)
variable state : std_logic := '0';
begin
if falling_edge(CLK) then
state := D;
Q <= state;
not_Q <= not state;
end if;
end process set_state;
end Behavioral;
I googled a lot for this. No chance. Any solutions?
It's not as you indicate in the title to the question that the internal signal to component my_Flipflop didn't trigger, it's that there is no method to provide a known non-meta value state - the not of 'U' is 'U'.
This is caused by the not operator. Refer to the not_table in the
body of package std_logic_1164:
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
See the changes and the added testbench:
library ieee; -- Added Context clause (MCVe)
use ieee.std_logic_1164.all;
entity D_Flipflop is
port (
D: in std_logic;
CLK: in std_logic;
Q: out std_logic;
not_Q: out std_logic := '0'
);
end entity;
architecture behavioral of D_Flipflop is
begin
set_state:
process (CLK) -- removed D from sensitivity list
variable state: std_logic := '0';
begin
if falling_edge(CLK) then
state := D;
Q <= state;
not_Q <= not state;
end if;
end process;
end architecture;
library ieee; -- added context clause
use ieee.std_logic_1164.all;
entity foo is
port (
CLK: in std_logic;
out_A: out std_logic -- removed extra ';'
);
end entity;
architecture Structure of foo is
component D_Flipflop is
port (
D: in std_logic;
CLK: in std_logic;
Q: out std_logic;
not_Q: out std_logic
);
end component;
-- signal D_A: std_logic; -- not used
signal qA: std_logic;
signal not_qA: std_logic := '1'; -- notice this didn't matter
begin
my_Flipflop:
D_Flipflop
port map (
not_qA,
CLK,
qA,
not_qA
);
out_A <= qA; -- Added
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity foo_tb is
end entity;
architecture fum of foo_tb is
signal CLK: std_logic := '0';
signal out_A: std_logic;
begin
DUT:
entity work.foo
port map (
CLK => CLK,
out_A => out_A
);
CLOCK:
process
begin
wait for 10 ns;
CLK <= not CLK;
if Now > 200 ns then
wait;
end if;
end process;
end architecture;
The not_Q output of the D_Flipflop has been initialized to '0' (it could have as easily been initialized to '1'). This represents the equivalent of a collector set for the Flip Flop on power up.
Now the Flip Flop can toggle - it has a known non-meta value on the D input.
This gives:
(clickable)