I am having trouble with a code I wrote. I keep getting an error when trying to simulate.
Warning
Warning C0007 : Architecture has unbound instance (ex. shifter2).
Here is my code. I am using DirectVHDL - PE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multi3 is
port (
C : in std_logic_vector (7 downto 0);
D : out std_logic_vector (10 downto 0));
end multi3;
architecture behavioral of multi3 is
component shifter
port (
Rin : in std_logic;
A : in std_logic_vector(7 downto 0);
B : out std_logic_vector(7 downto 0);
Lout: out std_logic);
end component;
signal E, F : std_logic_vector (7 downto 0);
signal L1, L2 : std_logic;
begin
shifter1 : shifter port map('0',C,E,L1);
shifter2 : shifter port map('0',E,F,L2);
D<=('0' & L1 & L2 & F)+C;
end Behavioral;
Related
I am making a 32 bit register with port and generic mapping. For some reason it says that the target signal Qt has 31 bits, while the input has 32 bits. Makes no sense right now. I looked through everything, and could not find how the Qt could be anything else than 32 bits since I declared the signal as signal Qt: std_logic_vector(31 downto 0);Any help is appreciated thanks.
I isolated the error line Qt <= D; and it still threw an exception. Down below is my minimally reproducible example.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
Did not realize that I had N: INTEGER:= 31 in the top file. When I changed the definition to N: INTEGER:= 32 the error disappeared. Sloppy coding on my part. I don't know why the tcl referenced this in the register file and not the top(lapfn) file. Is this because VHDL is written top down after port mapping, and it assumed the component from the top was the true bit-size?
entity LAPfn is
Port (resetn, clock, sclr, lap_db: in std_logic;
lap_select: in std_logic_vector (2 downto 0);
Data_in: in std_logic_vector (31 downto 0);
Lap_bits: out std_logic_vector (31 downto 0);
zlap: out std_logic;
cout: out std_logic_vector(2 downto 0));
end LAPfn;
architecture Behavioral of LAPfn is
component my_rege
generic (N: INTEGER:= 31);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
I am trying to run post synthesis functional simulation. When i run the code for behavioral simulation, i get the output and everything runs fine. Bu when i run the post synthesis i get the following error:
ERROR: [VRFC 10-3146] binding entity 'rippleadder_nbit' does not have generic 'n' [C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]
Can someone explain me what i need to do please. I am a novice in Vivado and very confused on how to use this
My Rippleadder Code is:
entity rippleadder_nbit is
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end rippleadder_nbit;
architecture Behavioral of rippleadder_nbit is
component fulladder port(
x_fa : in STD_LOGIC;
y_fa : in STD_LOGIC;
z_fa : in STD_LOGIC;
s_fa : out STD_LOGIC;
c_fa : out STD_LOGIC);
end component;
signal r: std_logic_vector(n downto 0);
begin
r(0) <= cin_ra;
cout_ra <= r(n);
FA: for i in 0 to n-1 generate
FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
end generate;
end Behavioral;
my testbench is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ripplenbit is
-- Port ( s: std_logic_vector(2 downto 0);
-- cout: std_logic);
end tb_ripplenbit;
architecture Behavioral of tb_ripplenbit is
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;
begin
a <= "0000", "0001" after 50 ns, "0101" after 100ns;
b <= "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;
UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);
end Behavioral;
In post-synthesis/post-implementation, the generics(constant) are deleted and usage of those generics are replaced with the constant value
In test bench, you had instance w.r.t to behavioural model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation
Source: Xilinx Forums
I am implementing the MIPS processor in VHDL using Quartus II, and one of my components is causing an error that has me completely baffled.
I have the following component:
library ieee;
use ieee.std_logic_1164.all;
entity HazardDetectionUnit is
port(
--Datapath inputs
IFIDrt : in std_logic_vector(4 downto 0);
IDEXrt : in std_logic_vector(4 downto 0);
IFIDrs : in std_logic_vector(4 downto 0);
--Controlpath inputs
IDEXMemRead : in std_logic;
PCWrite : out std_logic;
IFIDWrite : out std_logic;
IDEXFlush : out std_logic);
end HazardDetectionUnit;
architecture structural of HazardDetectionUnit is
signal same1 : std_logic;
signal same2 : std_logic;
signal NZ1 : std_logic;
signal stall : std_logic;
component comp5
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
comp_output : out std_logic);
end component;
component zerocomp5
port ( a : in std_logic_vector(4 downto 0);
zero : out std_logic);
end component;
begin
--Port Map
comparator1 : comp5 port map(IFIDrt, IDEXrt, same1);
comparator2 : comp5 port map(IDEXrt, IFIDrs, same2);
nonzero1 : zerocomp5 port map(IDEXrt, NZ1);
--Concurrent Signal Assignment
stall <= NZ1 and IDEXMemRead and (same1 or same2);
--Output Driver
PCWrite <= not(stall);
IFIDWrite <= not(stall);
IDEXFlush <= stall;
end structural;
I'm having an issue with the comp5 component. The error I'm getting is Error (12012): Port direction mismatch for entity "MIPS_PROCESSOR:inst|HazardDetectionUnit:inst22|comp5:comparator1" at port "comp_output". Upper entity is expecting "Input" pin while lower entity is using "Output" pin.
The sub-component comp5, which is a 5-bit equality comparator, is as follows:
library ieee;
use ieee.std_logic_1164.all;
entity comp5 is
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
comp_output : out std_logic
);
end comp5;
architecture structural of comp5 is
signal xor_out : std_logic_vector(4 downto 0);
component nxor2_5bit
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
o : out std_logic_vector(4 downto 0));
end component;
begin
--Port Map
xor_gate : nxor2_5bit port map(a, b, xor_out);
--Output Driver
comp_output <= xor_out(4) and xor_out(3) and xor_out(2) and xor_out(1) and xor_out(0);
end structural;
How is this possible? The comp5 component is clearly defined as having two 5-bit inputs, a and b, and a single one-bit output, comp_output. So why does the compiler insist that comp_output is actually an input?
I tried to debug the issue by implementing HazardDetectionUnit as a block diagram, but I got the same error.
I don't get it. comp5 is just a simple two-input, one-output logic unit. I've never had an error like this before, and I can't find any posts about a similar error. Would anyone be able to offer advice?
Edit: for completeness, here is the nxor2_5bit component:
--5-bit NXOR gate.
library ieee;
use ieee.std_logic_1164.all;
entity nxor2_5bit is
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
o : out std_logic_vector(4 downto 0));
end nxor2_5bit;
architecture structural of nxor2_5bit is
begin
--Output Driver
o <= not(a(4) xor b(4)) & not(a(3) xor b(3)) & not(a(2) xor b(2)) & not(a(1) xor b(1)) & not(a(0) xor b(0));
end structural;
When I try to compile this code I keep getting an error that says:
line 13: Error, 'std_logic' is not a known type.
Line 13 is Clock : IN std_logic;in the ALU_tb entity.
I am confused by this error, because it is my understanding that the reason for said error is normally a missing library/package. I'm almost sure I have the appropriate libraries and packages. Plus none of the other signals of type std_logic are getting errors.
If anyone could help me figure this out, I would greatly appreciate it.
-- VHDL Entity ALU.ALU_tb.symbol
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
ENTITY ALU_tb IS
PORT(
Clock : IN std_logic;
Reset_N : IN std_logic
);
-- Declarations
END ALU_tb ;
--
-- VHDL Architecture ALU.ALU_tb.struct
--
-- Created:
-- by - ClarkG.UNKNOWN (COELABS15)
-- at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY ALU;
ARCHITECTURE struct OF ALU_tb IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL A : std_logic_vector(31 DOWNTO 0);
SIGNAL ALUOp : std_logic_vector(3 DOWNTO 0);
SIGNAL B : std_logic_vector(31 DOWNTO 0);
SIGNAL Overflow : std_logic;
SIGNAL R : std_logic_vector(31 DOWNTO 0);
SIGNAL SHAMT : std_logic_vector(4 DOWNTO 0);
SIGNAL Zero : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Overflow : OUT std_logic ;
R : OUT std_logic_vector (31 DOWNTO 0);
Zero : OUT std_logic
);
END COMPONENT;
COMPONENT ALU_tester
PORT (
A : IN std_logic_vector (31 DOWNTO 0);
ALUOp : IN std_logic_vector (3 DOWNTO 0);
B : IN std_logic_vector (31 DOWNTO 0);
Clock : IN std_logic ;
Overflow : IN std_logic ;
R : IN std_logic_vector (31 DOWNTO 0);
Reset_N : IN std_logic ;
SHAMT : IN std_logic_vector (4 DOWNTO 0);
Zero : IN std_logic
);
END COMPONENT;
COMPONENT Test_transaction_generator
PORT (
Clock : IN std_logic ;
A : OUT std_logic_vector (31 DOWNTO 0);
ALUOp : OUT std_logic_vector (3 DOWNTO 0);
B : OUT std_logic_vector (31 DOWNTO 0);
SHAMT : OUT std_logic_vector (4 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ALU USE ENTITY ALU.ALU;
FOR ALL : ALU_tester USE ENTITY ALU.ALU_tester;
FOR ALL : Test_transaction_generator USE ENTITY ALU.Test_transaction_generator;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : ALU
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT,
Overflow => Overflow,
R => R,
Zero => Zero
);
U_1 : ALU_tester
PORT MAP (
A => A,
ALUOp => ALUOp,
B => B,
Clock => Clock,
Overflow => Overflow,
R => R,
Reset_N => Reset_N,
SHAMT => SHAMT,
Zero => Zero
);
U_2 : Test_transaction_generator
PORT MAP (
Clock => Clock,
A => A,
ALUOp => ALUOp,
B => B,
SHAMT => SHAMT
);
END struct;
The context clause comprised of a library clauses and use clauses should be moved to before the entity declaration instead of just before the architecture body. An entity and an architecture form a common declarative region allowing those library and use clauses to be in effect across both instead of just the architecture, as in your code presently.
You also don't appear to be using package std_logic_arith in the code you've shown. (The architecture only contains components).
At line 13, you have not yet imported the ieee libraries required to define std_logic which is why you're getting the error.
i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting
the line nos are bold ones in the code here.they are the portmap ones
Can anyone please help me out with this. it would be very kind of you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation: in std_logic_vector(2 downto 0);
Startt : in std_logic;
Ready : out std_logic;
Result_High : out std_logic_vector(3 downto 0);
Result_Low : out std_logic_vector(7 downto 0);
Errorsig : out std_logic;
Reset_n : in std_logic;
Clkk : in std_logic);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
-- And gate
component AND_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- OR Gate
component OR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate
component XOR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- Adder
COMPONENT adder4
PORT
(
C : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
C_out : OUT std_logic);
END COMPONENT;
-- Subtractor
COMPONENT Substractor4
PORT
(
br_in : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
E : out std_logic);
END COMPONENT;
-- Multiplier
COMPONENT mult4by4
port(operA, operB: in std_logic_vector(3 downto 0);
sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;
-- Division
COMPONENT Division
Port ( Dividend : in std_logic_vector(3 downto 0);
Divisor : in std_logic_vector(3 downto 0);
Start : in std_logic;
Clk : in std_logic;
Quotient : out std_logic_vector(3 downto 0);
Remainder : out std_logic_vector(3 downto 0);
Finish : out std_logic);
END COMPONENT;
begin
process(OperandA, OperandB, Startt, Operation) is
begin
case Operation is
when "000" =>
Result_High <= "XXXX";
when "001" =>
Result_High <= OperandA and OperandB;
when "010" =>
Result_High <= OperandA or OperandB;
when "011" =>
Result_High <= OperandA xor OperandB;
when "100" =>
-- Adder
**U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**
when "101" =>
-- Substractor & Error signal
**U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**
when "110" =>
-- multiplication
**U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**
when "111" =>
-- Division
if (OperandB ="0000") then
Errorsig <= '1';
else
**U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
end if;
when others =>
Errorsig <= '1';
end case;
end process;
end architecture Behavioral;
You cannot instantiate entities within a process.
Move all entity instantiations out of the process (into the architecture body) and work from there.
If you want to in instantiate component depending on the value of 'Operation', like the zennehoy wrote, you should instantiate components out of the process and in this case statement only use signal connected to this components in instantiations and link it to port you want.
For the length issue change the "Remainder : out std_logic_vector(3 downto 0);"
to "Remainder : out std_logic_vector(7 downto 0);"