Port direction mismatch in simple VHDL component - vhdl

Question

I am implementing the MIPS processor in VHDL using Quartus II, and one of my components is causing an error that has me completely baffled.
I have the following component:
library ieee;
use ieee.std_logic_1164.all;
entity HazardDetectionUnit is
port(
--Datapath inputs
IFIDrt : in std_logic_vector(4 downto 0);
IDEXrt : in std_logic_vector(4 downto 0);
IFIDrs : in std_logic_vector(4 downto 0);
--Controlpath inputs
IDEXMemRead : in std_logic;
PCWrite : out std_logic;
IFIDWrite : out std_logic;
IDEXFlush : out std_logic);
end HazardDetectionUnit;
architecture structural of HazardDetectionUnit is
signal same1 : std_logic;
signal same2 : std_logic;
signal NZ1 : std_logic;
signal stall : std_logic;
component comp5
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
comp_output : out std_logic);
end component;
component zerocomp5
port ( a : in std_logic_vector(4 downto 0);
zero : out std_logic);
end component;
begin
--Port Map
comparator1 : comp5 port map(IFIDrt, IDEXrt, same1);
comparator2 : comp5 port map(IDEXrt, IFIDrs, same2);
nonzero1 : zerocomp5 port map(IDEXrt, NZ1);
--Concurrent Signal Assignment
stall <= NZ1 and IDEXMemRead and (same1 or same2);
--Output Driver
PCWrite <= not(stall);
IFIDWrite <= not(stall);
IDEXFlush <= stall;
end structural;
I'm having an issue with the comp5 component. The error I'm getting is Error (12012): Port direction mismatch for entity "MIPS_PROCESSOR:inst|HazardDetectionUnit:inst22|comp5:comparator1" at port "comp_output". Upper entity is expecting "Input" pin while lower entity is using "Output" pin.
The sub-component comp5, which is a 5-bit equality comparator, is as follows:
library ieee;
use ieee.std_logic_1164.all;
entity comp5 is
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
comp_output : out std_logic
);
end comp5;
architecture structural of comp5 is
signal xor_out : std_logic_vector(4 downto 0);
component nxor2_5bit
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
o : out std_logic_vector(4 downto 0));
end component;
begin
--Port Map
xor_gate : nxor2_5bit port map(a, b, xor_out);
--Output Driver
comp_output <= xor_out(4) and xor_out(3) and xor_out(2) and xor_out(1) and xor_out(0);
end structural;
How is this possible? The comp5 component is clearly defined as having two 5-bit inputs, a and b, and a single one-bit output, comp_output. So why does the compiler insist that comp_output is actually an input?
I tried to debug the issue by implementing HazardDetectionUnit as a block diagram, but I got the same error.
I don't get it. comp5 is just a simple two-input, one-output logic unit. I've never had an error like this before, and I can't find any posts about a similar error. Would anyone be able to offer advice?
Edit: for completeness, here is the nxor2_5bit component:
--5-bit NXOR gate.
library ieee;
use ieee.std_logic_1164.all;
entity nxor2_5bit is
port( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
o : out std_logic_vector(4 downto 0));
end nxor2_5bit;
architecture structural of nxor2_5bit is
begin
--Output Driver
o <= not(a(4) xor b(4)) & not(a(3) xor b(3)) & not(a(2) xor b(2)) & not(a(1) xor b(1)) & not(a(0) xor b(0));
end structural;