I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.
I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.
can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??
what are the other methods to do that??
Regards
Ankit
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Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
I'm trying to synthetize any simple project in ISE for Spartan 6.
When I use Clocking Wizard for clk generator with f = 40 MHz (100Mhz external oscillator), XST says:
Timing Summary:
Speed Grade: -3
Minimum period: 9.482ns (Maximum Frequency: 105.458MHz)
Minimum input arrival time before clock: 2.623ns
Maximum output required time after clock: 3.597ns
Maximum combinational path delay: 5.194ns
OK, but when I change clk frequency in core generator to 100MHz, the response is Maximum Frequency is about 47MHz ...
What is wrong?
What is the right way to determine max frequency?
The reported maximum frequency in synthesis is only a rough estimation based on fanout, LUT levels, i/o-buffers, ...
The real timing analysis is done after Place & Route.
I have a project which already utilizes synthesis timing constraints (additional xcf-file), were XST reports f_max = 82 MHz. After P&R the design achieves 152 MHz :)
I need to divide the 50 MHz clock to 1.5 Mhz with 50% duty cycle using VHDL. For that I wanted to use a counter to count the number of 50 Mhz clock pulses until half of the 1.5 Mhz clock period i.e 16.6666 which is in decimal which I don't know how to implement in the code. Can any one please help me with it?
Thank you very much.
I'm not an expert in VHDL but I don't think you can get exactly to 1.5 MHz with synthesizable code. You could maybe get an average of 1.5 MHz if you vary how many clock cycles you wait on the 50 MHz clock until you raise the 1.5 MHz one.
If you only want code that can be simulated then of course you can just use arbitrary delays.
The approach you are suggesting will result in an approximation, which may of course be ok. If not, I would suggest you use instantiate a PLL or clock manager specific to the target technology.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.
I am trying to create a clock that only last 10 clock cycles from a 100 MHz signal. The clock will get enabled from a pulse signal.
-Every time the pulse signal goes to 1 clock2 follows 100 MHz clock1 for 10 cycles
I am working in VHDL
Do you mean that a 100 MHz clock is given as an input?
Assuming it is, a small state machine and a counter would be a good way to approach this. The state machine could have 2 states: idle and count. The next state logic would change the state from idle to count if the pulse signal is high. While in the count state the counter will increment and when the counter reaches ten, the state will move back to idle. The output logic will forward the clock signal to the output when in the count state. When in idle the output will be '0'.
For more information on making a state machine: How to implement state machines in VHDL
For more information on making a counter: Counters in VHDL
clock_input is the 100 MHz clock that is an input and clock_generated is the output.
The output logic will involve a multiplexer:
clock_generated <= clock_input when state=count else '0';