I am trying to create a clock that only last 10 clock cycles from a 100 MHz signal. The clock will get enabled from a pulse signal.
-Every time the pulse signal goes to 1 clock2 follows 100 MHz clock1 for 10 cycles
I am working in VHDL
Do you mean that a 100 MHz clock is given as an input?
Assuming it is, a small state machine and a counter would be a good way to approach this. The state machine could have 2 states: idle and count. The next state logic would change the state from idle to count if the pulse signal is high. While in the count state the counter will increment and when the counter reaches ten, the state will move back to idle. The output logic will forward the clock signal to the output when in the count state. When in idle the output will be '0'.
For more information on making a state machine: How to implement state machines in VHDL
For more information on making a counter: Counters in VHDL
clock_input is the 100 MHz clock that is an input and clock_generated is the output.
The output logic will involve a multiplexer:
clock_generated <= clock_input when state=count else '0';
Related
I have a piece of code like this in a process:
A <= '1';
A <= '0' after 5 sec;
Does it set A to 1 at first and then set A to 0 after 5 seconds? If not, what should I tweak?
No. It does this:
i) Schedule the setting of A to '1' on the next simulation (or delta) cycle.
ii) No. On second thoughts, don't do that. Instead, schedule the setting of A to '0' in 5 seconds time.
When a signal assignment operator is executed in VHDL, it does not drive the signal immediately. Instead it schedules a change on the signal (called an event) to be actioned some time in the future. If you do not specify a delay, then the event will be actioned on the next simulation (or delta) cycle. If VHDL encounters another signal assigment to the same signal, before it has actioned any previous ones, the corresponding events (usually) get deleted and replaced with the new one.
That might sound daft, but it is for good reasons. Replace your code with:
A <= '1';
wait for 5 sec;
A <= '0';
I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.
I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.
can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??
what are the other methods to do that??
Regards
Ankit
I know about rising_edge(clk) and when clk'event and clk ='1'.
i guess they detect edge.
but lets say i want to read the input when clk is high and in mid way. I guess I am able to write what I want to convey so how can we do that?
If I am not correct please explain.
thanks
In a testbench, or synthesisable into real hardware?
Assuming your clock has period clk_period, declared something like
constant clk_period : time := 100 ns; -- for 10 MHz
clk <= not clk after clk_period/2;
you can write testbench code like
wait until rising_edge(clk);
wait for clk_period/4;
value <= my_input;
However this is not synthesisable. In real hardware you need a different approach. Most FPGAs have clock generation modules (PLLs, DLLs, DCMs) which will allow you to generate phase shifted or inverted clocks, and you can use such a block to accomplish your task. More specific suggestions would depend on the actual FPGA you are using, and whether you have any faster clocks available.
For example, given clk and clk_2x which are phase aligned (so that each clk edge is a clk_2x rising edge) you can use the falling edge of clk_2x while clk is high.
process(clk_2x)
begin -- capture data
if falling_edge(clk_2x) then
if clk = '1' then
temp <= data_in;
end if;
end if;
end process;
process(clk)
begin -- resynch to main clock domain
if rising_edge(clk) then
value <= temp;
end if;
end process;
Alternative approaches can involve clocking the ADC from delayed, inverted or otherwise modified clocks, or using selectable delays in IOBs on the input data so that the (delayed) data is stable during the clock edge.
This is something that - without really good sim models of the external parts, can be quite tricky to get right in simulation, and needs thorough testing on actual hardware. I have sometimes used phase controllable clocks to external parts and mapped out the range of phases that worked before picking one phase or delay value for production.
attribute ram_style: string;
attribute ram_style of ram : signal is "distributed";
type dist_ram is array (0 to 99) of std_logic_vector(7 downto 0);
signal ram : dist_ram := (others => (others => '0'));
begin
--Pseudocode
PROCESS(Clk)
BEGIN
if(rising_edge(Clk)) then
ram(0) <= "0";
ram(2) <= "1";
ram(3) <= "2";
ram(4) <= "3";
ram(5) <= "1";
ram(6) <= "2";
...
...
ram(99) <= "3";
end if;
END PROCESS;
In the above scenario the complete ram gets updated in 1 clock cycle, however if i use a Block ram instead, i would require a minimum of 100 clock cycles to update the entire memory as opposed to 1 clock cycle when used as a distributed ram.
I also understand that it is not advisable to use the distributed ram for large
memory as it will eat up the FPGA resources.
So what is the best design for such situation (say for few KB ram) in order to achieve the best throughput.
Should i use block ram or distributed ram assuming Xilinx FPGA. Your suggestions are highly appreciated.
Thanks for your replies, let me make it a bit more clear.
My purpose is not for ram initialization,
i have 100 x 20 (8 bits) ram block which needs to be updated after
certain computation.
After these computations i have to store and then use it back for next iteration.
This is an iterative process and i am expected to finish atleast 2 iterations
within 3000 clk cycles.
if i use the block ram to store these coefficients then to just read and write
i would need atleast (100*20) cycles with some latency which will not meet my
requirement.
So how should i go about designing in this case.
What purpose are you trying to achieve? Do you really need to update the entire RAM on 1 clock cycle or can you break it into many clock cycles?
If you can break it up into many clocks you could do something like:
PROCESS(Clk)
BEGIN
if(rising_edge(Clk)) then
ram(index) <= index;
index <= index + 1;
end if;
END PROCESS;
You can initialize a block ram as well. The specifics of this depend on your FPGA vendor. So for a Xilinx FPGA look at this article:
http://www.xilinx.com/itp/xilinx10/isehelp/pce_p_initialize_blockram.htm
If you really cannot afford to break it up into multiple clocks and you want to "initialize" it more than once then you will need to use distributed ram the way you did above.
I need to create a VHDL code for this situation:
**Draw a control circuit that generates a pulse signal with:
fixed working frequency (100 KHz)
variable working cycle
The phase difference should be increased or decreased by the direction of the spin of a rotary control of 8 bits.**
Additional info:
D = t (on) / T
D = working cycle
t (on) = Time the activated signal lasts (rotary control of 8 bits)
T = signal period (constant)
You seem to be wanting to generate a mark:space ratio of between 1:255 and 255:1, so you will need a clock frequency of 256 * 100kHz.
An 8 bit incrementing counter can be left free-running clocked at that rate.
Now have a flop that is SET when the counter overflows from X'FF to X'00 and that CLEARS when the timer value makes the transition from N-1 to N. Where N is the 8 bit value on your duty cycle setting control and controls the width of the mark.
The threshold controlled flop's output is your variable duty cycle 100kHz.