I need to divide the 50 MHz clock to 1.5 Mhz with 50% duty cycle using VHDL. For that I wanted to use a counter to count the number of 50 Mhz clock pulses until half of the 1.5 Mhz clock period i.e 16.6666 which is in decimal which I don't know how to implement in the code. Can any one please help me with it?
Thank you very much.
I'm not an expert in VHDL but I don't think you can get exactly to 1.5 MHz with synthesizable code. You could maybe get an average of 1.5 MHz if you vary how many clock cycles you wait on the 50 MHz clock until you raise the 1.5 MHz one.
If you only want code that can be simulated then of course you can just use arbitrary delays.
The approach you are suggesting will result in an approximation, which may of course be ok. If not, I would suggest you use instantiate a PLL or clock manager specific to the target technology.
Related
Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
Is it possible to generate a 33.3Mhz clock from a 50Mhz clock in VHDL? If so, how?
Many thanks
Danny
Adding to this... with making a PLL in Qsys whats the difference between the "rst" that is always included in the PLL and asynchronous "rst" that is selectable when configuring the PLL?
No. Like Brian said in his comment (actually could be answer) just instantiate a PLL module with 33.3MHz clk output.
Note: your 50MHz and 33.3MHz clocks will now be in different clock domains. So take special care when signals are crossing between them. I would start by googling synchronizer ;)
I have a clock of 100 mhz. I want to use DCM to create a clock of 78 mhz.
I think I should use two DCM, where the output of first DCM goes into the second DCM but I don't know if this will work.
Best Regards
Rather than using a DCM directly you can investigate using a Direct Digital Frequency Synthesizer (DDFS). It amounts to an accumulator that is incremented by a constant count value. You can control the precision by the size of the accumulator.
It is helpful if there is as much disparity between the accumulator clock and the generated frequency as possible. Consider using a DCM to scale the 100MHz up to the highest speed you can run a counter of the necessary width and still meet timing for your target device. There will be some jitter equal to one period of whatever clock is driving the accumulator but the average frequency can be made very close to 78 MHz.
accum_freq = 100 MHz * DCM_MULTIPLIER
accum_size = ceil(log2(accum_freq / (78 MHz * tolerance)))
increment = 78 MHz / accum_freq * 2**accum_size
accum = accum + increment
You then tap off the MSB of the accumulator to get your synthesized 78 MHz clock.
You can either manually compute these constants for use as magic numbers or do the arithmetic natively in VHDL to define the size and increment as machine computed constants. By reducing the tolerance you will increase the required size of the accumulator. Start off with 0.01% (0.0001) and see if it is satisfactory.
What device are you targeting? On a Spartan-6 the DCM_CLKGEN allows a multiplier of 39 and a divider of 50, which gets you your 78MHz.
If you set your multiplier to 7 and your divider to 9 you'll be able to get to 77.77 MHz. Will that work for you?
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.