Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
Related
I read somewhere that to find the real latency of the ram you can use the following rule :
1/((RAMspeed/2)/1000) x CL = True Latency in nanoseconds
ie for DDR1 with 400Mhz clock speed, is it logical to me to divide by 2 to get the FSB speed or the real bus speed which is 200Mhz in this case. So the rule above seems to be correct for the DDR1.
From the other side, DDR2 also doubles the freq of the bus in relation to the previous DDR1 generation (ie 4 bits per clock cycle) according the article "What Every Programmer Should Know About Memory".
So, in the case of a DDR2 with a 800Mhz clock speed, to find the "True Latency" the above rule should be accordingly changed to
1/((RAMspeed/4)/1000) x CL = True Latency in nanoseconds
Is that correct? Because in all the cases I read that the correct way is to take RAMspeed/2 no matter if it's DDR, DDR2, DDR3 or DDR4.
Which is the correct way to get the true latency?
The CAS latency is in memory-bus clock cycles. This is always one half the transfers-per-second number. e.g. DDR3-1600 has a memory clock of 800MHz, doing 1600M transfers per second (during a burst transfer).
DDR2, DDR3, and DDR4 still use a double-pumped 64-bit memory bus (transferring data on the rising and falling edges of the clock signal), not quad-pumped. This is why they're still called Double Data-Rate (DDR) SDRAM.
The FSB speed has nothing to do with it.
On old CPUs without integrated memory controllers, i.e. systems that actually have an FSB, its frequency is often configurable (in the BIOS) separately from the memory speed. See Front Side Bus and RAM speed; on even older systems, the FSB and memory clocks were synchronous.
Normally systems were designed with a fast enough FSB to keep up with the memory controller. Running the FSB at the same clock speed as the memory can reduce latency by avoiding buffering between clock domains.
So yes, the CAS latency in seconds is cycle_count / frequency, or more like your formula
1000ns/us * CL / RAMspeed * 2 transfers/clock, where RAMspeed is in mega-transfers per second.
Higher CL numbers at a higher memory frequency often work out to a similar absolute latency (in seconds). In other words, modern RAM has higher CAS latency timing numbers because more clock cycles happen in the same amount of time.
Bandwidth has vastly improved, while latency has stayed nearly constant, according to these graphs from Crucial which explain CL vs. frequency.
Of course this is not "the memory latency", or the "true" memory latency.
It's the CAS latency of the DRAM itself, and is the most important factor in latency between the memory controller and the DRAM, but is only a part of the latency between a CPU core and memory. There is non-negligible latency inside the CPU between the core and uncore (L3 and memory controller). Uncore is Intel terminology; IDK what AMD calls the parts of the memory hierarchy in their various microarchitectures.
Especially many-core Xeon CPUs have significant latency to L3 / memory controller, because of the large ring bus(es) connecting all the cores. A many-core Xeon has worse L3 and memory latency than a similar dual or quad-core with the same memory and CPU clock frequencies.
This extra latency actually limits single-thread / single-core bandwidth on a big Xeon to worse than a laptop CPU, because a single core can't keep enough requests in flight to fill the memory pipeline with that much latency. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?.
Ok I found the answer.
Everytime the manufacturers increased the memory clock speed they did it in a constant rate which always was the double (2x) of the FSB clock speed. ie
MEM CLK FSB
-------------------
DDR200 100 MHz
DDR266 133 MHz
DDR333 166 MHz
DDR400 200 MHz
DDR2-400 200 MHz
DDR2-533 266 MHz
DDR2-667 333 MHz
DDR2-800 400 MHz
DDR2-1066 533 MHz
DDR3-800 400 MHz
DDR3-1066 533 MHz
DDR3-1333 666 MHz
DDR3-1600 800 MHz
So, the memory module has always the double speed of the FSB.
Using a Stratix II FPGA is it possible to generate a clock output with a frequency much higher than 200MHz? (Up to 400 or 500MHz) If so how can I achieve this?
I used a PLL to generate 200MHz out of a 100MHz clock and this seems to work. But turning the PLL to 250MHz will make the TimeQuest Timing Analyzer reporting a negative setup slack for the PLL in the slow model. So I wonder if there is a better way to generate such high frequency clock outputs...
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
I need to divide the 50 MHz clock to 1.5 Mhz with 50% duty cycle using VHDL. For that I wanted to use a counter to count the number of 50 Mhz clock pulses until half of the 1.5 Mhz clock period i.e 16.6666 which is in decimal which I don't know how to implement in the code. Can any one please help me with it?
Thank you very much.
I'm not an expert in VHDL but I don't think you can get exactly to 1.5 MHz with synthesizable code. You could maybe get an average of 1.5 MHz if you vary how many clock cycles you wait on the 50 MHz clock until you raise the 1.5 MHz one.
If you only want code that can be simulated then of course you can just use arbitrary delays.
The approach you are suggesting will result in an approximation, which may of course be ok. If not, I would suggest you use instantiate a PLL or clock manager specific to the target technology.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.