The entity was created by the IDE and seemingly randomly started giving me a syntax error. I tried restarting IDE since that works sometimes, didn't work this time.
The compiler says Syntax error near "end". The problem line is end design1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity design1 is
Port ( Reg_A : in STD_LOGIC_VECTOR(31 downto 0);
Reg_B : in STD_LOGIC_VECTOR(31 downto 0);
Op_Sel : in STD_LOGIC_VECTOR(3 downto 0);
C_In : in STD_LOGIC;
C_Out : out STD_LOGIC;
ALU_Out : out STD_LOGIC_VECTOR(31 downto 0);
end design1;
architecture Behavioral of design1 is
begin
process is
begin
if(Op_Sel(3) = '0') then
if(Op_Sel(2) = '0') then --performing arithmetic
if(Op_Sel(1 downto 0) = "00") then --transfer A
elsif(Op_Sel(1 downto 0) = "01") then --increment A
elsif(Op_Sel(1 downto 0) = "10") then --decrement A
elsif(Op_Sel(1 downto 0) = "11") then --add
end if;
end if;
elsif(Op_Sel(2) = '1') then --performing logic operations
if(Op_Sel(1 downto 0) = "00") then --Not A
if(Op_Sel(1 downto 0) = "01") then --A and B
if(Op_Sel(1 downto 0) = "10") then --A or B
if(Op_Sel(1 downto 0) = "11") then --A xor B
elsif(Op_Sel(3) = '1') then --Shifting
if(Op_Sel(2) = '0') then --right shift
elsif(Op_Sel(2) = '1' then --left shift
end if;
end if;
end process;
end Behavioral;
Related
I'm trying to write a 4-bit multiplier with VHDL. This is the code I wrote:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplier_8bit_2 is
Port ( clk : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end multiplier_8bit_2;
architecture Behavioral of multiplier_8bit_2 is
begin
process(clk, A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if A'event or B'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
end if;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
end Behavioral;
It can be executed in simulation and it works, but when I try to synthesize it, I get:
unsupported Clock statement.
If you just want a multiplier with 4 bit arguments, then code it without clk as follows. You do not need a'event or b'event.
process(A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
OTOH, if you wanted a multiplier and a flip-flop, then code the following. You have no need for A or B on the sensitivity list.
process(clk)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if clk = '1' and clk'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end if;
end process;
I was trying to do a work and this error is boring me, i pass to a new project teste.vhdl and this keep happening, i need to have two barriers of clock one for input and another to output, to use timequest with combinational logic.
The 'and' is just a example.
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY teste IS
PORT(
clock : in std_logic;
clear : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0)
);
END teste;
ARCHITECTURE comportamento OF teste IS
signal a1,b1,s1 : std_logic_vector(3 downto 0);
begin
FF_in: process(clock.clear)
begin
if clear = '1' then
a1 <= "0000";
b1 <= "0000";
elsif clock'event and clock = '1' then
a1 <= a;
b1 <= b;
end if;
end process;
s1 <= a1 and b1;
FF_out: process(clock.clear)
begin
if clear = '1' then
s <= "0000";
elsif clock'event and clock = '1' then
s <= s1;
end if;
end process;
END comportamento;
You have used a . Rather than , in the process sensitivity list. Using a . Is trying to access a record field.
What I am trying to do is as follows:
I am taking few elements of an array, comparing them with a fixed value and trying to create a vector out of it.
Here is a piece of code:
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A"));
....
end process;
...
This should give something like sel_sig_cmd = 1000 or may be 1011 etc. But this is not working. Is there any alternative to this code? cheers Tahir
This is because the = function in VHDL returns a boolean, not a std_logic.
In VHDL '93, there is no tidy way to do this, other than set each bit manually:
sel_sig_cmd(3) <= '1' when (ins_f_array(4) = x"3A") else '0'
sel_sig_cmd(2) <= '1' when (ins_f_array(3) = x"3A") else '0'
-- etc
but in VHDL 2008, there are the relational operators (?= ?/= etc), that return std_logic on compare. So your code becomes:
sel_sig_cmd <= ( (ins_f_array(4) ?= x"3A")
& (ins_f_array(3) ?= x"3A")
& (ins_f_array(2) ?= x"3A")
& (ins_f_array(1) ?= x"3A") );
The answer from Tricky is a good one to follow. However, if you want to implement it in a process, then the process can be rewritten as follows :
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process(ins_f_array(4 downto 1)) begin
if ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&
(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A")) then
sel_sig_cmd <= "XXXX" -- Enter your desired value
....
end process;
...
This process would be tedious though as it has to cover all the 16 possibilities of the "if condition".
Another implementation is to use an if condition for each bit as follows :
architecture behav of main_ent is
...
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0);
...
process(ins_f_array(4 downto 1)) begin
if (ins_f_array(4) = x"3A") then
sel_sig_cmd(3) <= "X" -- Enter your desired value
else
sel_sig_cmd(3) <= "X" -- Enter your desired value
end if;
-- Repeat for other bits
....
end process;
...
You can overload the "=" operator :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity;
architecture behav of tb is
function "=" (Left, Right: std_logic_vector) return std_logic is
begin
if (Left = Right) then
return '1';
else
return '0';
end if;
end function "=";
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array := (x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07",x"08");
signal sel_sig_cmd : std_logic_vector(3 downto 0);
begin
process (ins_f_array(1 to 4)) begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3) = x"3A")&(ins_f_array(2) = x"3A")&(ins_f_array(1) = x"3A"));
end process;
process
begin
wait for 10 us;
for i in 0 to 8 loop
ins_f_array(i) <= std_logic_vector(unsigned(ins_f_array(i)) + 1);
end loop;
end process;
end architecture;
I'm working on a MIPS-like CPU in VHDL with Xilinx Vivado. I have a component for my BranchControl module, which goes like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BranchControl is
Port ( PL : in STD_LOGIC;
BC : in STD_LOGIC_VECTOR(3 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
AD : in STD_LOGIC_VECTOR (31 downto 0);
Flags : in STD_LOGIC_VECTOR(3 downto 0);
PCLoad : out STD_LOGIC;
PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end BranchControl;
architecture Behavioral of branchcontrol is
signal Z,N,P,C,V, T: std_logic;
begin
Z <= Flags(3); -- zero flag
N <= Flags(2); -- negative flag
P <= not N and not Z; -- positive flag
C <= FLags(1); -- carry flag
V <= Flags(0); -- overflow flag
T <=
'1' when (PL = '1') and (BC = "0000") and (Flags = "XXXX") else -- B
'1' when (PL = '1') and (BC = "0010") and (Flags = "1XXX") else -- BEQ
'1' when (PL = '1') and (BC = "0011") and (Flags = "0XXX") else -- BNE
'1' when (PL = '1') and (BC = "0100") and (Flags = "00XX") else -- BGT
'1' when (PL = '1') and (BC = "0101") and (Flags = "11XX") else -- BGE
'1' when (PL = '1') and (BC = "0110") and (Flags = "01XX") else -- BLT
'1' when (PL = '1') and (BC = "0111") and (Flags = "11XX") else -- BLE
'0';
with T select
PCValue <= PC+AD when '1',
PC when others;
PCLoad <= T;
end Behavioral;
I am writing a simulation to test the BranchControl component, and ensure it is working as I intend. Here's my simulation:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SimulBranchControl is
end SimulBranchControl;
architecture Behavioral of SimulBranchControl is
component BranchControl is
Port ( PL : in STD_LOGIC;
BC : in STD_LOGIC_VECTOR( 3 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
AD : in STD_LOGIC_VECTOR (31 downto 0);
Flags : in STD_LOGIC_VECTOR(3 downto 0);
PCLoad : out STD_LOGIC;
PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal iPL : STD_LOGIC;
signal iBC : STD_LOGIC_VECTOR(3 downto 0);
signal iPC : STD_LOGIC_VECTOR(31 downto 0);
signal iAD : STD_LOGIC_VECTOR(31 downto 0);
signal iFlags : STD_LOGIC_VECTOR(3 downto 0);
signal clock : std_logic := '0';
begin
process
begin
wait for 50 ns;
clock <= not clock;
end process;
process
begin
wait until clock'event and clock='0';
iPL<='1'; iBC<="0010"; iPC<=x"00000000"; iAD<=x"00000001"; iFlags<="0000";
end process;
BC0: BranchControl port map(iPL=>PL, iBC=>BC, iPC=>PC, iAD=>AD, iFlags=>Flags);
end Behavioral;
For some reason, when I try and run the simulation in Vivado, I get a set of errors on the elaboration step:
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/BranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity BranchControl
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity SimulBranchControl
ERROR: [VRFC 10-719] formal port/generic <ipl> is not declared in <branchcontrol> [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-704] formal pl has no actual or default value [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:8]
INFO: [VRFC 10-240] VHDL file /home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd ignored due to errors
Now, from what I understand this means that my entity BranchControl, and my my component of it on the Simulation have incompatible declarations, but I don't see how this is true, they seem exactly the same to me. Here's a screenshot of Vivado giving me the error.
Why is this happening? What am I doing wrong?
Your component mapping in the instantiation is the wrong way around; it should be:
bc0: BranchControl port map (pl => ipl, bc => ibc, pc => ipc, ad => iad, flags => iflags);
I'm trying to create an entity to fill an array from signals, but I'm getting the following error: near text "=" expecting "(" or " ' " or "."
This is my vhdl code
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity decryptionarray is
port(
clk: in std_logic;
key_in: in std_logic_vector(7 downto 0);
encrypted_data : in std_logic_vector(127 downto 0);
encrypted_data_in : in std_logic_vector(127 downto 0);
decryption_key: out std_logic_vector(7 downto 0)
);
end entity decryptionarray;
architecture bhv of decryptionarray is
type deckeyarray is array (0 to 10) of std_logic_vector(127 downto 0);
signal dkey, keyin : std_logic_vector(7 downto 0);
signal edatain, edata : std_logic_vector(127 downto 0);
begin
P0:process(clk) is
begin
if(deckeyarray(10)/=null) then
for j in 0 to 10 loop
deckeyarray(j)=null;
end loop;
else
keyin <= key_in;
edata <= encrypted_data;
edatain <= encrypted_data_in ;
dkey <= decryption_key ;
end if;
end process P0;
end architecture bhv;
VHDL does not have compare with null as in deckeyarray(10)/=null, and deckeyarray is a type, not a signal.
To check for all 0's you can do:
use ieee.numeric_std.all;
...
type deckeyarray_t is array (0 to 10) of std_logic_vector(127 downto 0);
signal deckeyarray : deckeyarray_t;
...
if unsigned(deckeyarray(10)) = 0 then
The compare can also be made without the unsigned and numeric_std, but using deckeyarray(10) = (deckeyarray(10)'range => '0') instead.
To fill with all 0's you can do:
deckeyarray(j) <= (others => '0');
Note that the decryption_key output port is read in dkey <= decryption_key;, which does not make sense.