I was trying to do a work and this error is boring me, i pass to a new project teste.vhdl and this keep happening, i need to have two barriers of clock one for input and another to output, to use timequest with combinational logic.
The 'and' is just a example.
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY teste IS
PORT(
clock : in std_logic;
clear : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0)
);
END teste;
ARCHITECTURE comportamento OF teste IS
signal a1,b1,s1 : std_logic_vector(3 downto 0);
begin
FF_in: process(clock.clear)
begin
if clear = '1' then
a1 <= "0000";
b1 <= "0000";
elsif clock'event and clock = '1' then
a1 <= a;
b1 <= b;
end if;
end process;
s1 <= a1 and b1;
FF_out: process(clock.clear)
begin
if clear = '1' then
s <= "0000";
elsif clock'event and clock = '1' then
s <= s1;
end if;
end process;
END comportamento;
You have used a . Rather than , in the process sensitivity list. Using a . Is trying to access a record field.
Related
I've been asked at the university to make a 4-bit bidirectional shift register. I did it first this way:
-- bidirektionale shift register mit data-load und serielle(R/L) output
library ieee;
use ieee.std_logic_1164.all;
entity bi_shift_reg is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Serial Shift-Right output
s_dout_L: out std_logic -- Serial Shift-Left output
);
end bi_shift_reg;
architecture arch of bi_shift_reg is
begin
process(clk,set,n_reset)
begin
-- reset (low aktiv)
if n_reset = '0' then dout <= "0000";
-- set
elsif set = '1' then dout <= "1111";
-- data-load
elsif(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
dout <= din;
-- shift right
elsif(rising_edge(clk) and sR = '1') then
s_dout_R <= din(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
s_dout_L <= din(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end process;
end arch;
but then I heard that I needed to use my previous coded D-Flipflop as a component for the shift register. So my question is: since I have new inputs (data_load,shift_left and shift_right) and outputs(Serial Shift-Right, Serial Shift-Left) how can I add them in my code along with the d-ff component? is it possible to use a component and process together ?
This is my d-ff code with asynchronous activ-low reset and asynchronous set:
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk,set,n_reset)
variable temp: std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
How can I use my flipflop to achieve the same result as the code for the shift-register ?
Thank you in advance for your answers :D
After several good questions in the comment track by the OP, it is reasonable to post some design that can serve as an example for a solution.
Please note, that there was not any precise specification of the intended operation, e.g. what is priority between different inputs, and how should timing be for outputs, so the code below is provided with the intention of showing some VHDL structures that may works as a template for further update by the OP.
--###############################################################################
-- d_flipflop
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk, set, n_reset)
variable temp : std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
--###############################################################################
-- bi_shiftReg_ff
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port(din : in std_logic_vector(3 downto 0);
set, n_reset : in std_logic;
sR, sL : in std_logic; -- Shift-Right/Shift-Left
data_load : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(3 downto 0);
s_dout_R : out std_logic; -- Shift-Right output
s_dout_L : out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
-- FF component
component d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end component;
-- FF data input
signal d : std_logic_vector(3 downto 0);
-- FF data output
signal q : std_logic_vector(3 downto 0);
signal qn : std_logic_vector(3 downto 0); -- Unused, but included for completness
begin
-- Combinatorial process, thus making gates only
process (all)
begin
-- data-load
if (data_load = '1') then
d <= din;
-- shift right; priority over shift left
elsif (sR = '1') then
d <= '0' & q(q'left downto 1); -- Discard right-most bit in the right shift
-- shift left
elsif (sL = '1') then
d <= q(q'left - 1 downto 0) & '0'; -- Discard left-most bit in the left shift
end if;
end process;
-- State held in FFs
GEN_REG : for i in 0 to 3 generate
REGX : d_flipflop port map
(d(i), clk, set, n_reset, q(i), qn(i));
end generate;
-- Outputs drive
dout <= q;
s_dout_R <= q(q'right); -- Bit 0, but shown with VHDL attributes
s_dout_L <= q(q'left); -- Bit 3, --||--
end arch;
--###############################################################################
-- EOF
I am new to VHDL and I have an issue writing a 4-bit comparator.
When I want to compare different sets of inputs there is only one output for all of them. And I don't know how to solve this problem. I want to have only one output and need to show 0000 if A is less than B, and 1111 if A is greater than B, and 0011 if they are equal. Can anybody please help me with my problem?
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp_4 is
port ( A:IN STD_LOGIC_VECTOR(3 downto 0);
B:IN STD_LOGIC_VECTOR(3 downto 0);
output:OUT STD_LOGIC_VECTOR(3 downto 0)
);
end comp_4;
architecture dataflow of comp_4 is
begin
process
begin
if (A=B) then
output <= "0011";
elsif (A>B) then
output <= "1111";
else
output <= "0000";
end if;
wait;
end process;
end dataflow;
And also my test bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Comparator_test IS
END Comparator_test;
ARCHITECTURE Ctest OF Comparator_test IS
COMPONENT comp_4 IS
port( A:IN STD_LOGIC_VECTOR(3 downto 0);
B:IN STD_LOGIC_VECTOR(3 downto 0);
output:OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
SIGNAL a : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL b : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL c : STD_LOGIC_VECTOR(3 downto 0);
BEGIN
uut : comp_4 PORT MAP(a, b , c);
a <= "0100" , "1111" After 10 NS;
b <= "0101" , "1100" AFTER 10 NS;
END Ctest;
And my simulation looks like this:
You need to put the inputs on the sensitivity list.
Note, wait; stops the process infinitely (only in simulation, it cannot be synthesized).
Solution 1:
Use the process' sensitivity list, and remove wait;.
architecture dataflow of comp_4 is
begin
process(A, B)
begin
if (A = B) then
output <= "0011";
elsif (A > B) then
output <= "1111";
else
output <= "0000";
end if;
end process;
end dataflow;
Solution 2:
Use the sensitivity list of wait.
architecture dataflow of comp_4 is
begin
process
begin
if (A = B) then
output <= "0011";
elsif (A > B) then
output <= "1111";
else
output <= "0000";
end if;
wait on A, B;
end process;
end dataflow;
How do I make this register design synchronous?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY register1 IS
PORT (
d_in : IN std_logic_vector(7 DOWNTO 0);
load : IN std_logic;
clear : IN std_logic;
reg1 : INOUT std_logic_vector(7 DOWNTO 0)
);
END register1;
ARCHITECTURE toplevel OF register1 IS
BEGIN
PROCESS (load, clear)
BEGIN
IF clear = '1' THEN
reg1 <= "00000000";
ELSIF load = '1' THEN
reg1 <= d_in;
ELSIF load = '0' THEN
reg1 <= reg1;
END IF;
END PROCESS;
END ARCHITECTURE toplevel;
To have a synchronous design you need to add a clock you want to sync to and then perform your logic e.g. on the rising edge
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY register1 IS
PORT (
clk_i : IN std_logic;
d_in : IN std_logic_vector(7 DOWNTO 0);
load : IN std_logic;
clear : IN std_logic;
reg1 : INOUT std_logic_vector(7 DOWNTO 0)
);
END register1;
ARCHITECTURE toplevel OF register1 IS
BEGIN
PROCESS (clk_i, clear) -- Note the change of the sensitivity list
BEGIN
IF clear = '1' THEN
reg1 <= "00000000";
ELSIF rising_edge(clk_i) THEN
IF load = '1' THEN
reg1 <= d_in;
ELSE
reg1 <= reg1;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE toplevel;
Note that this still is async clear.
Btw. why is reg1 of type INOUT?
In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;.
I don't think it is a syntax error. But Quartus shows an error at that point.
I don`t understand why it's an error.
Can anyone provide information:
-- Error--
Error (10500): VHDL syntax error at S8BT16B.vhd(35) near text "when"; expecting ";"
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50 : in std_logic;
clk_baud : in std_logic;
main_reset : in std_logic;
enable : in std_logic;
sig_in : in signed (7 downto 0);
sig_out : out complex;
valid_output : out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg : state;
signal sig_out_real : signed(15 downto 0);
begin
state_change : process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active : process(clk_baud, state_reg)
begin
if (state_reg = idle) then
sig_out_real <="0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif (state_reg = start and enable = '1') then
sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
You code does not present a Minimal, Complete, and Verifiable example.
The package fft_package presumably containing the type declaration for complex is not present.
The declaration for signed_converted_input is also not present.
A sequential conditional signal assignment statement is only available in VHDL-2008.
There's a good argument to be made that the Synopsys packages std_logic_arith and std_logic_signed are not compatible with IEEE Std 1076-2008's defined package std_logic_1164. It's possible they've been re-written to accomidate the new definitions of std_logic_vector and std_ulogic vector, although not if they work without -2008 compatibility, without some serious automagic on the part of ALDEC.
If passing a -2008 compatibility flag doesn't fix things for you the simplest thing you can do is replace the sequential conditional signal assignment statement with two simple signal assignment statements inside an if statement:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package fft_package is
type complex is record
sig_real: signed (15 downto 0);
sig_imaginary: signed (15 downto 0);
end record;
constant signed_converted_input: signed (15 downto 0) := (others => '0');
end package;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50: in std_logic;
clk_baud: in std_logic;
main_reset: in std_logic;
enable: in std_logic;
sig_in: in signed (7 downto 0);
sig_out: out complex;
valid_output: out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg: state;
signal sig_out_real: signed(15 downto 0);
begin
state_change:
process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active:
process(clk_baud, state_reg)
begin
if state_reg = idle then
sig_out_real <= "0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif state_reg = start and enable = '1' then
-- sig_out_real <= X"00" & sig_in when sig_in(7)='0' else
-- X"ff" & sig_in;
if sig_in(7) = '0' then
sig_out_real <= X"00" & sig_in;
else
sig_out_real <= X"ff" & sig_in;
end if;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
This code analyzes, elaborates and simulates (to show there are no length mismatches without regards to sig_in(7) = '0') while any claim to it's functionality is not made. The length looks right in the assignments to sig_out_real.
And of course without seeing the actual contents of your package fft_package claims to syntax and semantic validity can't be absolutely made (the faux package and your modified code are consistent with each other).
I am doing a project in college and want to produce a triangular wave using a DAC2904 and a Spartan 3 xc3s5000 board.
I have written code for it but is not working.
I don't know may be it is the problem in code or in my ucf file:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity traingular is
Port (
clk : in std_logic; -- on board clock
reset : in std_logic;
dac_clk : out std_logic; -- clk for dac module
output : out std_logic_vector(13 downto 0); -- output to dac
wr_dac : out std_logic -- pulse given to write pin of dac ic.
);
end traingular;
architecture Behavioral of traingular is
signal counter : unsigned(3 downto 0);
signal divide : std_logic_vector(15 downto 0);
signal sampling_clk , clk_s : std_logic;
signal decade : std_logic_vector(3 downto 0);
-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much
begin
process(clk, reset)
begin
if (reset = '1' ) then
decade <= (others => '0');
elsif (clk' event and clk = '1') then
if (decade = "1010") then
decade <= (others => '0');
else
decade <= std_logic_vector(unsigned(decade) + 1);
end if;
end if;
end process;
clk_s <= '1' when decade = "1010" else
'0';
process(clk_s , reset)
begin
if (reset='1') then
divide <= (others => '0');
elsif (clk_s'event and clk_s = '1') then
divide <= std_logic_vector(unsigned(divide) + 1);
end if;
end process;
sampling_clk <= divide(2);
-- input click is still fast so clock is divided further
dac_clk <= sampling_clk;
wr_dac <= sampling_clk;
process(clk , reset)
begin
-- code below is for counter which will further feed to dac to produce traingular wave.
if (reset = '1' ) then
counter <= (others => '0');
elsif (clk' event and clk = '1') then
if (counter = "1010") then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
output <= "0000000000" & std_logic_vector(counter); -- output to dac.
end Behavioral;
So, can you guys tell me what is the problem in my code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tri_wave is
Port ( clk : in STD_LOGIC;
rst :in STD_LOGIC;
up_step_size,down_step_size:in std_logic_vector(2 downto 0);
dac_out : out STD_LOGIC_VECTOR (7 downto 0));
end tri_wave;
architecture Behavioral of tri_wave is
signal dac_wav:std_logic_vector(7 downto 0);
signal count:std_logic_vector(7 downto 0);
signal dir:std_logic:='0';
begin
process(clk,rst,dir)
begin
if rst='1' then
count<=(others=>'0');
elsif dir='0' then
if clk'event and clk='1' then
if count="01111111" then
dir<='1' ;
else
count<= count + up_step_size;
end if;
end if;
elsif dir='1' then
if clk'event and clk='1' then
if count="10000000" then
dir<='0' ;
else
count<= count - down_step_size;
end if;
end if;
end if;
end process;
--dac_out<=count;
dac_out<=count(count'high) & count(6 downto 0);
end Behavioral;
i think this code gives u better idea just creaet tb and simulae i odelsim u will get it.