Can VHDL synthesize clk'event? - vhdl

I'm trying to write a 4-bit multiplier with VHDL. This is the code I wrote:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplier_8bit_2 is
Port ( clk : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end multiplier_8bit_2;
architecture Behavioral of multiplier_8bit_2 is
begin
process(clk, A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if A'event or B'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
end if;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
end Behavioral;
It can be executed in simulation and it works, but when I try to synthesize it, I get:
unsupported Clock statement.

If you just want a multiplier with 4 bit arguments, then code it without clk as follows. You do not need a'event or b'event.
process(A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
OTOH, if you wanted a multiplier and a flip-flop, then code the following. You have no need for A or B on the sensitivity list.
process(clk)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if clk = '1' and clk'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end if;
end process;

Related

How to declare an array of arrays in the test bench of a VHDL code?

I have an array of arrays defined as the input to my entity. I used a package to define the array of arrays. In the test bench, I included that package and declared the component in the architecture but there is an error saying "formal port x does not exist in entity average. Please compare the definition of block average to its component declaration and its instantion to detect the mismatch."
Attaching the declarations below. Please help.
-- the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package vpkg is
type m_array is array(1 downto 0, 1 downto 0) of std_logic_vector(7 downto 0);
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity average is
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end average;
architecture avg_arch of average is
signal sum : std_logic_vector(8 downto 0) := (others => '0');
begin
process(x):
for I in 0 to 1 loop
for J in 0 to 1 loop
sum <= sum + ('0' + x(I,J));
end loop;
end loop;
end process;
y <= std_logic_vector(to_signed(to_integer(signed(sum) / 4),8));
end avg_arch;
--the test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity tb_average is
-- Port ( );
end tb_average;
architecture tb_average_arch of tb_average is
component average
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end component;
signal x : m_array;
signal clk : std_logic := '0';
signal y : std_logic_vector(7 downto 0);
begin
average_1 : average Port Map (x => x,clk => clk,y=>y);
input_proc : process
begin
wait for 100ns;
x(0,0) <= "00001001";
x(0,1) <= "00000110";
x(1,0) <= "00000011";
x(1,1) <= "00000001";
wait;
end process;
clk_proc : process
begin
wait for 100ns;
loop
clk <= '1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end loop;
end process;
end tb_average_arch;

VHDL compiler giving me syntax error at end of entity definition

The entity was created by the IDE and seemingly randomly started giving me a syntax error. I tried restarting IDE since that works sometimes, didn't work this time.
The compiler says Syntax error near "end". The problem line is end design1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity design1 is
Port ( Reg_A : in STD_LOGIC_VECTOR(31 downto 0);
Reg_B : in STD_LOGIC_VECTOR(31 downto 0);
Op_Sel : in STD_LOGIC_VECTOR(3 downto 0);
C_In : in STD_LOGIC;
C_Out : out STD_LOGIC;
ALU_Out : out STD_LOGIC_VECTOR(31 downto 0);
end design1;
architecture Behavioral of design1 is
begin
process is
begin
if(Op_Sel(3) = '0') then
if(Op_Sel(2) = '0') then --performing arithmetic
if(Op_Sel(1 downto 0) = "00") then --transfer A
elsif(Op_Sel(1 downto 0) = "01") then --increment A
elsif(Op_Sel(1 downto 0) = "10") then --decrement A
elsif(Op_Sel(1 downto 0) = "11") then --add
end if;
end if;
elsif(Op_Sel(2) = '1') then --performing logic operations
if(Op_Sel(1 downto 0) = "00") then --Not A
if(Op_Sel(1 downto 0) = "01") then --A and B
if(Op_Sel(1 downto 0) = "10") then --A or B
if(Op_Sel(1 downto 0) = "11") then --A xor B
elsif(Op_Sel(3) = '1') then --Shifting
if(Op_Sel(2) = '0') then --right shift
elsif(Op_Sel(2) = '1' then --left shift
end if;
end if;
end process;
end Behavioral;

Adding two bit_vector in VHDL return error "(vcom-1581) No feasible entries for infix operator '+'."

This is my code for converting binary to BCD in VHDL
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : bit_vector(3 downto 0) := "0110";
variable bcdout_temp : bit_vector(4 downto 0);
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := ('0' & bin) + ('0' & temp);
else
bcdout_temp := ('0' & bin);
end if;
end if;
bcdout <= bcdout_temp;
end process;
end bin2bcdarch;
The problem is when i am trying to add the two bit_vector in the line
bcdout_temp := ('0' & bin) + ('0' & temp);
using "+" operator, that I get the error
(vcom-1581) No feasible entries for infix operator '+'.
Now, I looked in the web and most of the solutions are for when I use std_logic_vector.
The code works fine if I use std_logic_vector but not when I use bit_vector.
Is there any solution to the problem as to why I am getting the error?
You can add bit vectors if you use ieee.numeric_bit_unsigned.all which is part of VHDL-2008. The numeric_std package you're using does not define addition for bit vector.
If you find your old CAD lab software doesn't support numeric_bit_unsigned you can use type conversions, numeric_bit contains declarations for types signed and unsigned:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd is
port (bin : in bit_vector(3 downto 0) := "0000";
clk : in bit;
bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;
architecture bin2bcdarch of bin2bcd is
begin
process(clk)
variable gt9 : bit;
variable temp : unsigned(3 downto 0) := "0110"; -- was bit_vector
variable bcdout_temp : unsigned(4 downto 0); -- was bit vector
begin
if clk'event and clk = '1' then
gt9 := bin(3) and(bin(2) or bin(1));
if gt9 = '1' then
bcdout_temp := '0' & unsigned(bin) + ('0' & temp); -- type conversion
else
bcdout_temp := '0' & unsigned(bin); -- type conversion
end if;
end if;
bcdout <= bit_vector(bcdout_temp); -- type conversion
end process;
end bin2bcdarch;
Note temp can also be class constant instead of variable, it's not assigned other than an initial value.
From your comments using WARP2 to synthesis (presumably CPLDs) I recall that it was originally developed to use AHDL as input description and that support for VHDL and Verilog were an afterthought.
You're likely seeing limitations based on what VHDL constructs map to AHDL constructs that are supported for synthesis.
The way to deal with such limitations may be to describe troublesome parts of designs as a dataflow description:
entity bin2bcd is
port (
bin: in bit_vector(3 downto 0);
clk: in bit;
bcdout: out bit_vector(4 downto 0)
);
end entity bin2bcd;
architecture dataflow of bin2bcd is
signal bcdout_temp: bit_vector(4 downto 0);
begin
bcdout_temp(4) <= bin(3) and ( bin(2) or bin(1) ); -- gt9
bcdout_temp(3) <= not bcdout_temp(4) and bin(3); -- zero if gt9
bcdout_temp(2) <= ( bin(3) and bin(2) and bin(1)) or
(not bin(3) and bin(2));
bcdout_temp(1) <= ( bcdout_temp(4) and not bin(1)) or -- gt9 XOR bin(1)
(not bcdout_temp(4) and bin(1));
bcdout_temp(0) <= bin(0); -- doesn't change
REG5:
process (clk)
begin
if clk'event and clk = '1' then
bcdout <= bcdout_temp;
end if;
end process;
end architecture;
While there's no guarantee of this would work better (although likely) it also simulates as VHDL with a testbench:
library ieee;
use ieee.numeric_bit.all;
entity bin2bcd_tb is
end entity;
architecture foo of bin2bcd_tb is
signal bin: bit_vector(3 downto 0);
signal clk: bit;
signal bcdout: bit_vector(4 downto 0);
begin
DUT:
entity work. bin2bcd (dataflow)
port map (
bin => bin,
clk => clk,
bcdout => bcdout
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if now > 160 ns then
wait;
end if;
end process;
STIMULI:
process
begin
for i in 0 to 2 ** bin'length - 1 loop
bin <= bit_vector(to_unsigned(i, bin'length));
wait for 10 ns;
end loop;
wait;
end process;
end architecture;
And shows it gives the right results:
bin is displayed in decimal while bcdout is displayed in hex.

vhdl code for producig triangular wave using DAC2904 is not working

I am doing a project in college and want to produce a triangular wave using a DAC2904 and a Spartan 3 xc3s5000 board.
I have written code for it but is not working.
I don't know may be it is the problem in code or in my ucf file:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity traingular is
Port (
clk : in std_logic; -- on board clock
reset : in std_logic;
dac_clk : out std_logic; -- clk for dac module
output : out std_logic_vector(13 downto 0); -- output to dac
wr_dac : out std_logic -- pulse given to write pin of dac ic.
);
end traingular;
architecture Behavioral of traingular is
signal counter : unsigned(3 downto 0);
signal divide : std_logic_vector(15 downto 0);
signal sampling_clk , clk_s : std_logic;
signal decade : std_logic_vector(3 downto 0);
-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much
begin
process(clk, reset)
begin
if (reset = '1' ) then
decade <= (others => '0');
elsif (clk' event and clk = '1') then
if (decade = "1010") then
decade <= (others => '0');
else
decade <= std_logic_vector(unsigned(decade) + 1);
end if;
end if;
end process;
clk_s <= '1' when decade = "1010" else
'0';
process(clk_s , reset)
begin
if (reset='1') then
divide <= (others => '0');
elsif (clk_s'event and clk_s = '1') then
divide <= std_logic_vector(unsigned(divide) + 1);
end if;
end process;
sampling_clk <= divide(2);
-- input click is still fast so clock is divided further
dac_clk <= sampling_clk;
wr_dac <= sampling_clk;
process(clk , reset)
begin
-- code below is for counter which will further feed to dac to produce traingular wave.
if (reset = '1' ) then
counter <= (others => '0');
elsif (clk' event and clk = '1') then
if (counter = "1010") then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
output <= "0000000000" & std_logic_vector(counter); -- output to dac.
end Behavioral;
So, can you guys tell me what is the problem in my code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tri_wave is
Port ( clk : in STD_LOGIC;
rst :in STD_LOGIC;
up_step_size,down_step_size:in std_logic_vector(2 downto 0);
dac_out : out STD_LOGIC_VECTOR (7 downto 0));
end tri_wave;
architecture Behavioral of tri_wave is
signal dac_wav:std_logic_vector(7 downto 0);
signal count:std_logic_vector(7 downto 0);
signal dir:std_logic:='0';
begin
process(clk,rst,dir)
begin
if rst='1' then
count<=(others=>'0');
elsif dir='0' then
if clk'event and clk='1' then
if count="01111111" then
dir<='1' ;
else
count<= count + up_step_size;
end if;
end if;
elsif dir='1' then
if clk'event and clk='1' then
if count="10000000" then
dir<='0' ;
else
count<= count - down_step_size;
end if;
end if;
end if;
end process;
--dac_out<=count;
dac_out<=count(count'high) & count(6 downto 0);
end Behavioral;
i think this code gives u better idea just creaet tb and simulae i odelsim u will get it.

VHDL code does not synthesize

I have written 2 state machines in my VHDL code. The simulation works fine, but the code does not synthesize. Any help would be appreciated. Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pulse_width is
Port ( clk : in STD_LOGIC;
timer2:in std_logic;
input: in STD_LOGIC;
result: inout STD_LOGIC_VECTOR (15 downto 0);
SEL_LINE: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_out: out STD_LOGIC_VECTOR (23 downto 0):=x"000000");
end pulse_width;
architecture Behavioral of pulse_width is
TYPE count_states is (s0,s0_dash,s1,s2,s3,s1_dash);
SIGNAL current_state, next_state : count_states := s0 ;
TYPE write_states is (ws0,ws0_dash,ws1,ws2,ws3,ws4);
SIGNAL current_state1, next_state1 : write_states := ws0 ;
TYPE index_array is ARRAY(integer range 0 to 65535) of std_logic_vector(15 downto 0);
SIGNAL mem: index_array;
SIGNAL count: std_logic_vector(15 downto 0):=x"0000";
SHARED VARIABLE j: integer:=0;
SHARED VARIABLE a,i: integer:=1;
SIGNAL flag,push_data,push_first,push_final,push_pulses,rw_first,rw_end: std_logic:='0';
SIGNAL y_clk_input ,y_clk_timer2, enable_count: std_logic:='0';
SIGNAL first,final: std_logic_vector(15 downto 0):= x"0001";
begin
-- Pulse width count
process (clk)
begin
if rising_edge(clk) then
current_state<=next_state;
current_state1<=next_state1;
end if;
end process;
process(input,SEL_LINE,current_state)
begin
------------------------------------------------------------------------
case current_state is
when s0 =>
if(input='1') then
next_state<=s1;
else
next_state<=s0;
end if;
when s1 =>
flag<='0';
if input='1' then
count <= count+ x"0001";
next_state<=s1_dash;
else
next_state<=s2;
end if;
when s1_dash =>
if input='1' then
count <= count+ x"0001";
next_state<=s1;
else
next_state<=s2;
end if;
when s2 =>
result <= count;
next_state<=s3;
when s3=>
count <= x"0000";
next_state<=s0;
enable_count<='0';
when others =>
next_state<=s0;
end case;
--------------------------------------------------------------------------
case current_state1 is
when ws0 =>
if (result>x"0000") then
next_state1<=ws1;
else
next_state1<=ws0_dash;
end if;
when ws0_dash =>
if (result>x"0000") then
next_state1<=ws1;
else
next_state1<=ws0;
end if;
when ws1=>
if rw_first='1' and rw_end='1' then
next_state1<=ws0;
else
mem(a) <= result;
a:=a+1;
final<=final+x"0001";
next_state1<=ws2;
end if;
when ws2 =>
next_state1<=ws0;
result<=x"0000";
when others =>
next_state1<=ws0;
end case;
end process;
I eventually need to implement three state machines.
The math you're trying to do in the asynchronous state logic is not registered and won't synthesize well. You need to re-arrange your state logic so statements like:
count <= count+ x"0001";
...
final<=final+x"0001";
...are synchronous and not 'free running' in an asynchronous loop.
The problem is that you read and write the same signals in one combinational process.
Either put everything in one clocked (synchronous) process
Or: use explicit registers: count_next <= count + x"0001";
Not related to your error, but still worth paying attention to:
You have a ton of unused signals and shared variables:
push_data,push_first,push_final,push_pulses, y_clk_input ,y_clk_timer2, first, i,j
This is confusing for anybody trying to read your code. 1
The packages STD_LOGIC_arith and STD_LOGIC_unsigned are deprecated

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