Can VHDL synthesize clk'event? - vhdl

Question

I'm trying to write a 4-bit multiplier with VHDL. This is the code I wrote:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplier_8bit_2 is
Port ( clk : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end multiplier_8bit_2;
architecture Behavioral of multiplier_8bit_2 is
begin
process(clk, A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if A'event or B'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
end if;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
end Behavioral;
It can be executed in simulation and it works, but when I try to synthesize it, I get:
unsupported Clock statement.

Answer 1

If you just want a multiplier with 4 bit arguments, then code it without clk as follows. You do not need a'event or b'event.
process(A, B)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end process;
OTOH, if you wanted a multiplier and a flip-flop, then code the following. You have no need for A or B on the sensitivity list.
process(clk)
variable sum_result : unsigned(8 downto 0) := (others => '0');
begin
if clk = '1' and clk'event then
sum_result:=(others => '0');
for i in 0 to 3 loop
if B(i)='1' then
sum_result:=sum_result+shift_left(b"00000"&unsigned(A),i);
end if;
end loop;
Y<=STD_LOGIC_VECTOR(sum_result(7 downto 0));
end if;
end process;