near text "=" expecting "(" or " ' " or "." - vhdl

Question

I'm trying to create an entity to fill an array from signals, but I'm getting the following error: near text "=" expecting "(" or " ' " or "."
This is my vhdl code
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity decryptionarray is
port(
clk: in std_logic;
key_in: in std_logic_vector(7 downto 0);
encrypted_data : in std_logic_vector(127 downto 0);
encrypted_data_in : in std_logic_vector(127 downto 0);
decryption_key: out std_logic_vector(7 downto 0)
);
end entity decryptionarray;
architecture bhv of decryptionarray is
type deckeyarray is array (0 to 10) of std_logic_vector(127 downto 0);
signal dkey, keyin : std_logic_vector(7 downto 0);
signal edatain, edata : std_logic_vector(127 downto 0);
begin
P0:process(clk) is
begin
if(deckeyarray(10)/=null) then
for j in 0 to 10 loop
deckeyarray(j)=null;
end loop;
else
keyin <= key_in;
edata <= encrypted_data;
edatain <= encrypted_data_in ;
dkey <= decryption_key ;
end if;
end process P0;
end architecture bhv;

Answer 1

VHDL does not have compare with null as in deckeyarray(10)/=null, and deckeyarray is a type, not a signal.
To check for all 0's you can do:
use ieee.numeric_std.all;
...
type deckeyarray_t is array (0 to 10) of std_logic_vector(127 downto 0);
signal deckeyarray : deckeyarray_t;
...
if unsigned(deckeyarray(10)) = 0 then
The compare can also be made without the unsigned and numeric_std, but using deckeyarray(10) = (deckeyarray(10)'range => '0') instead.
To fill with all 0's you can do:
deckeyarray(j) <= (others => '0');
Note that the decryption_key output port is read in dkey <= decryption_key;, which does not make sense.