I have a vivando project and when I try to create a port map in one of my vhdl programs,I get errors that I don't know how to resolve - vhdl

Question

I have this vhdl file that I am trying to make a port map for in vivando, but I keep getting errors that I don't understand. I'm relatively new to vhdl and would appreciate any assistance in helping me figure out what I need to change.
This is the program with the port map
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DispAlu4 IS
PORT(
a: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Input SW[7..4]: a[3..0]
b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Input SW[3..0]: b[3..0]
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Input SW[15..14]: control[1..0]
led15: OUT STD_LOGIC; -- Output LED[15]: overflow
led17: OUT STD_LOGIC; -- Output LED[17]: zero
led16: OUT STD_LOGIC; -- Output LED[16]: cOut
an: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Output AN[7..0]: '0' enabled
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) -- Output HEX[6..0]: result[3..0]
);
END DispAlu4;
ARCHITECTURE behavioral OF DispAlu4 IS
COMPONENT Alu4
PORT(
a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
overflow: OUT STD_LOGIC;
zero: OUT STD_LOGIC;
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT Bin2Hex
PORT(
bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
SIGNAL overflow_sig: STD_LOGIC;
SIGNAL zero_sig: STD_LOGIC;
SIGNAL carry_sig: STD_LOGIC;
SIGNAL result_sig: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1: Alu4 PORT MAP (a, b, control_sig => control, overflow_sig, zero_sig, result_sig, carry_sig); #port map that has errors
END behavioral;
These are the other programs referenced in it:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Alu4 IS
GENERIC( CONSTANT N: INTEGER := 4; -- 4 bits ALU
CONSTANT Z: STD_LOGIC_VECTOR(3 DOWNTO 1) := "000" -- 3 Zeros
);
PORT(
a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
overflow: OUT STD_LOGIC;
zero: OUT STD_LOGIC;
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END Alu4;
ARCHITECTURE behavioral OF Alu4 IS
COMPONENT Alu1
PORT(
a: IN STD_LOGIC;
b: IN STD_LOGIC;
cIn: IN STD_LOGIC;
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC
);
END COMPONENT;
SIGNAL carry_sig: STD_LOGIC_VECTOR(N DOWNTO 0); -- carry_sig(N) = MSB cOut
SIGNAL result_sig: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
process (a, b, control)
BEGIN
case control is
WHEN "000" =>
result_sig <= a AND b;
WHEN "001" =>
result_sig <= a OR b;
WHEN "010" =>
result_sig <= carry_sig;
WHEN "011" =>
result_sig <= carry_sig;
WHEN "100" =>
result_sig <= NOT a;
WHEN "101" =>
result_sig <= a XOR b;
WHEN "110" =>
result_sig <= carry_sig;
WHEN "111" =>
result_sig <= NOT b;
WHEN others =>
NULL;
END case;
END process;
END behavioral;
2nd program
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Bin2Hex IS
PORT(
bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4-bit binary inputs
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) --7-segment hex display
);
END Bin2Hex;
ARCHITECTURE behavioral OF Bin2Hex IS
BEGIN
WITH bin SELECT
hex <= "1000000" WHEN "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" WHEN "0011", --3
"0011001" WHEN "0100", --4
"0010010" WHEN "0101", --5
"0000010" WHEN "0110", --6
"1111000" WHEN "0111", --7
"0000000" WHEN "1000", --8
"0010000" WHEN "1001", --9
"0001000" WHEN "1010", --A
"0000011" WHEN "1011", --b
"0100110" WHEN "1100", --C
"0100001" WHEN "1101", --d
"0000110" WHEN "1110", --E
"0001110" WHEN "1111", --F
"1111111" when others;
END behavioral;