Why am I not seeing an output when I synthesize? - vhdl

I have been working on a lab assignment that is practically complete, but am running into an issue where I am not seeing an output when synthesizing. I have 7 blocks, that when tested individually display the correct output. How is it that I wouldn't get any output at all when using the top module and test bench files? Below is my top module, followed by my test bench as I suspect the problem may be there. I've looked it over and can't pinpoint anything I may have done wrong. Any help would be appreciated.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is port(
x,y : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
z : out std_logic_vector(7 downto 0)
);
end top_module;
architecture behavior of top_module is
signal bwAnd, bwOr, bwXor, add, subtract, bwComplement, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6 : std_logic_vector(7 downto 0);
component BW_And is port(
x,y : in std_logic_vector(7 downto 0);
z1 : out std_logic_vector(7 downto 0)
);
end component;
component BW_Rr is port(
x,y : in std_logic_vector(7 downto 0);
z2 : out std_logic_vector(7 downto 0)
);
end component;
component BW_Xor is port(
x,y : in std_logic_vector(7 downto 0);
z3 : out std_logic_vector(7 downto 0)
);
end component;
component full_adder_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "00000000";
sum, cout: out std_logic_vector(7 downto 0)
);
end component;
component full_subtractor_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "11111111";
difference, cout: out std_logic_vector(7 downto 0)
);
end component;
component Complement is port(
x : in std_logic_vector(7 downto 0);
z4 : out std_logic_vector(7 downto 0)
);
end component;
component mux is port(
z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
mux_out : out std_logic_vector(7 downto 0)
);
end component;
begin
--instantiating components and mapping ports
c0: BW_And port map(x => x, y => y, z1 => bwAnd);
c1: BW_Or port map(x => x, y => y, z2 => bwOr);
c2: BW_Xor port map(x => x, y => y, z3 => bwXor);
c3: full_adder_8 port map(x => x, y => y, sum => add);
c4: full_subtractor_8 port map(x => x, y => y, difference => subtract);
c5: Complement port map(x => x, z4 => bwComplement);
c6: mux port map(z1 => mux_in1, z2 => mux_in2, z3 => mux_in3, sum => mux_in4, difference => mux_in5, z4 =>mux_in6, opcode => opcode, mux_out => z);
end behavior;
Test Bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab4 is
end Lab4;
architecture behavior of Lab4 is
component top_module is port(
x,y : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
z : out std_logic_vector(7 downto 0)
);
end component;
signal test_x : std_logic_vector(7 downto 0);
signal test_y : std_logic_vector(7 downto 0);
signal test_opcode : std_logic_vector(2 downto 0) := "000";
signal test_z : std_logic_vector(7 downto 0);
begin
uut: top_module port map (x => test_x, y => test_y, opcode => test_opcode, z => test_z);
sim_proc : process
begin
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "000";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "001";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "010";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "011";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "100";
wait for 100 ns;
test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "101";
end process;
end behavior;
Entities for each component:
entity BW_And is port(
x,y : in std_logic_vector(7 downto 0);
z1 : out std_logic_vector(7 downto 0)
);
end BW_And;
entity BW_Or is port(
x,y : in std_logic_vector(7 downto 0);
z2 : out std_logic_vector(7 downto 0)
);
end BW_Or;
entity BW_Xor is port(
x,y : in std_logic_vector(7 downto 0);
z3 : out std_logic_vector(7 downto 0)
);
end BW_Xor;
entity full_adder_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "00000000";
sum, cout: out std_logic_vector(7 downto 0)
);
end full_adder_8;
entity full_subtractor_8 is port(
x,y : in std_logic_vector(7 downto 0);
cin : in std_logic_vector(7 downto 0) := "11111111";
difference, cout: out std_logic_vector(7 downto 0)
);
end full_subtractor_8;
entity Complement is port(
x : in std_logic_vector(7 downto 0);
z4 : out std_logic_vector(7 downto 0)
);
end Complement;
entity mux is port(
z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(2 downto 0);
mux_out : out std_logic_vector(7 downto 0)
);
end mux;

I realized where my problem was after all. The issue was with my mux file. In my process, I only passed "opcode" neglecting to pass in all of the inputs.
Before:
process (opcode)
.
.
.
end process;
After:
process (z1,z2,z3,sum,difference,z4,opcode)
.
.
.
end process;

Related

I have a vivando project and when I try to create a port map in one of my vhdl programs,I get errors that I don't know how to resolve

I have this vhdl file that I am trying to make a port map for in vivando, but I keep getting errors that I don't understand. I'm relatively new to vhdl and would appreciate any assistance in helping me figure out what I need to change.
This is the program with the port map
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DispAlu4 IS
PORT(
a: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Input SW[7..4]: a[3..0]
b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Input SW[3..0]: b[3..0]
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Input SW[15..14]: control[1..0]
led15: OUT STD_LOGIC; -- Output LED[15]: overflow
led17: OUT STD_LOGIC; -- Output LED[17]: zero
led16: OUT STD_LOGIC; -- Output LED[16]: cOut
an: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Output AN[7..0]: '0' enabled
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) -- Output HEX[6..0]: result[3..0]
);
END DispAlu4;
ARCHITECTURE behavioral OF DispAlu4 IS
COMPONENT Alu4
PORT(
a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
overflow: OUT STD_LOGIC;
zero: OUT STD_LOGIC;
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT Bin2Hex
PORT(
bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
SIGNAL overflow_sig: STD_LOGIC;
SIGNAL zero_sig: STD_LOGIC;
SIGNAL carry_sig: STD_LOGIC;
SIGNAL result_sig: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1: Alu4 PORT MAP (a, b, control_sig => control, overflow_sig, zero_sig, result_sig, carry_sig); #port map that has errors
END behavioral;
These are the other programs referenced in it:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Alu4 IS
GENERIC( CONSTANT N: INTEGER := 4; -- 4 bits ALU
CONSTANT Z: STD_LOGIC_VECTOR(3 DOWNTO 1) := "000" -- 3 Zeros
);
PORT(
a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
overflow: OUT STD_LOGIC;
zero: OUT STD_LOGIC;
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END Alu4;
ARCHITECTURE behavioral OF Alu4 IS
COMPONENT Alu1
PORT(
a: IN STD_LOGIC;
b: IN STD_LOGIC;
cIn: IN STD_LOGIC;
control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cOut: OUT STD_LOGIC;
result: OUT STD_LOGIC
);
END COMPONENT;
SIGNAL carry_sig: STD_LOGIC_VECTOR(N DOWNTO 0); -- carry_sig(N) = MSB cOut
SIGNAL result_sig: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
process (a, b, control)
BEGIN
case control is
WHEN "000" =>
result_sig <= a AND b;
WHEN "001" =>
result_sig <= a OR b;
WHEN "010" =>
result_sig <= carry_sig;
WHEN "011" =>
result_sig <= carry_sig;
WHEN "100" =>
result_sig <= NOT a;
WHEN "101" =>
result_sig <= a XOR b;
WHEN "110" =>
result_sig <= carry_sig;
WHEN "111" =>
result_sig <= NOT b;
WHEN others =>
NULL;
END case;
END process;
END behavioral;
2nd program
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Bin2Hex IS
PORT(
bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4-bit binary inputs
hex: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) --7-segment hex display
);
END Bin2Hex;
ARCHITECTURE behavioral OF Bin2Hex IS
BEGIN
WITH bin SELECT
hex <= "1000000" WHEN "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" WHEN "0011", --3
"0011001" WHEN "0100", --4
"0010010" WHEN "0101", --5
"0000010" WHEN "0110", --6
"1111000" WHEN "0111", --7
"0000000" WHEN "1000", --8
"0010000" WHEN "1001", --9
"0001000" WHEN "1010", --A
"0000011" WHEN "1011", --b
"0100110" WHEN "1100", --C
"0100001" WHEN "1101", --d
"0000110" WHEN "1110", --E
"0001110" WHEN "1111", --F
"1111111" when others;
END behavioral;

Accumulator Design

Thank you, everyone, here I have modified the post. I have written a simple code VHDL for trap filter by using different components for each task. The below is sample code where different components are used and all the other components are working perfectly except accumulator component(acc1), the out signal remains zero. In the acc1 one component I am trying to to make two accumulators where the first acc1 (output of the first accumulator) is the input for the acc2. As the other components are working so here I only showed the port mapping of acc1 component in the code along the test bench.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use ieee.fixed_pkg.all;
ENTITY TRAPFILTER IS
GENERIC (
K : integer :=80;
L : integer :=200
--M : signed(9 downto 0) := to_signed(5)
);
PORT
(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DATAOUT : OUT STD_LOGIC_VECTOR(24 DOWNTO 0);
DATAOUT1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); ---
READY : OUT STD_LOGIC;
Soutout : out std_logic_vector(23 downto 0);
Koutout : out std_logic_vector(13 downto 0);
Loutout : out std_logic_vector(13 downto 0)
);
END ENTITY TRAPFILTER;
ARCHITECTURE RTL OF TRAPFILTER IS
constant M : sfixed(1 downto -2) := to_sfixed(0.01,1,-2);
type Sdelay_reg is array(0 to 2) OF signed(21 downto 0);
signal S_reg : Sdelay_reg :=(others=>(others=>'0'));
-------------------------------------------------------------
signal y_reg0 : signed (27 downto 0) :=(others=>'0');
signal y_reg1 : signed (31 downto 0) :=(others=>'0');
-----------------------------------------------------------
signal in_reg : signed(13 downto 0) :=(others=>'0');
signal out_reg : signed(DATAOUT'length-1 downto 0) :=
(others=>'0');
-- ----------------------------------------------------------
signal fs : std_logic :='0';
--------------------kdelay component----------------------------------
component kdelay is
GENERIC (
K : integer :=80;
L : integer :=200
);
port
(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto 0);
kout : OUT STD_LOGIC_VECTOR (13 downto 0)
);
end component;
signal kout : std_logic_vector (13 downto 0) :=(others=>
'0');
--------------------Ldelay component----------------------
------------
component Ldelay is
GENERIC (
K : integer :=80;
L : integer :=200
);
port
(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto
0);
Lout : OUT STD_LOGIC_VECTOR (13 downto
0)
);
end component;
signal Lout : std_logic_vector (13 downto 0) :=
(others=>'0');
---------------------------------------------------
component sub_mult is
port(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto
0);
Sout : out STD_LOGIC_VECTOR (23
downto 0)
);
end component;
signal Sout : std_logic_vector (23
downto 0) :=(others=>'0');
-------------------------------------------
component accum1 is
port(
clk : in std_logic ;
rst : in std_logic;
din : in
STD_LOGIC_VECTOR (23 downto 0);
Acout : out
STD_LOGIC_VECTOR (24 downto 0);
Acout1 : out
STD_LOGIC_VECTOR (25 downto 0)
);
end component;
signal acc_out1 : std_logic_vector (24 downto 0) :=(others=>'0');
signal acc_out2 : std_logic_vector (25 downto 0) :=(others=>'0');
----------------------------------------------------------------
BEGIN
Koutout <= Kout;
Loutout <= Lout;
Soutout <= Sout;
in_reg <= signed (DATAIN);
DATAOUT <= acc_out1;--std_logic_vector(out_reg);
DATAOUT1 <= acc_out2;
utacc1:component accum1
port map(
clk => clk,
rst => rst,--: in std_logic;
din => Sout, --: OUT STD_LOGIC_VECTOR
(13 downto 0);
Acout => acc_out1, -- : out STD_LOGIC_VECTOR (24 downto 0)
Acout1 => acc_out2
);
END RTL;
------------------------Accum1 component----------------------------------
library IEEEieee;`
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use ieee.fixed_pkg.all;
entity accum1 is port(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (23 downto 0);
Acout : out STD_LOGIC_VECTOR (24 downto 0);
Acout1 : out STD_LOGIC_VECTOR (25 downto 0)
);
end entity;
architecture rtl of accum1 is
signal dout : signed(24 downto 0) :=(others=>'0');
signal datain : signed(23 downto 0) :=(others=>'0');
signal dout2 : signed(25 downto 0) :=(others=>'0');
begin
datain <= signed(din);
process(clk,rst,datain)
variable cm : signed(24 downto 0);
begin
if(rst='1' ) then
dout <= (others=>'0');
dout2 <= (others=>'0');
cm := (others=>'0');
elsif(rising_edge(clk) and clk'event) then
cm := datain + cm;
dout <= cm ;
dout2 <= dout2 + cm ;
end if;
end process;
Acout <= std_logic_vector(dout);
Acout1 <= std_logic_vector(dout2) ;
end rtl;
------------------------test bench only trapfilter comppnent portmapping
uttrap5:component TRAPFILTER
PORT MAP
(
CLK => TestClk, -- : IN STD_LOGIC;
RST => i_rstb, -- : IN STD_LOGIC;
DATAIN => odata, --odata, -- : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DATAOUT => trap_out, --: OUT STD_LOGIC_VECTOR(13 DOWNTO 0); ---
DATAOUT1 => trap_out1,
READY => trap_ready, --: OUT STD_LOGIC
Koutout => Koutout, --out std_logic_vector(23 downto 0);
Loutout => loutout, --: out std_logic_vector(13 downto 0);
Soutout => Soutout
);
enter image description here
Several issues in your code
You don't need datain in your sensitivity list.
When using rising_edge, you don't need event
The variable cm will not keep their value when re-enter the process. Use signal instead or just use value of dout.
I am really understand what is your dout2 logic?

How to initialize a VHDL std_logic_vector to "0001"

i want to initialize my vectors from "0001" instead of "0000" default cause i'm doing an "automatic" 4 Bit multiplier and (x * 0) isn't useful, so
I want to skip the "0000" value.
Here is my Entity:
ENTITY multiplier IS
PORT (
clk, rst : IN std_logic;
q, r : INOUT std_logic_vector (3 DOWNTO 0) := "0001"; -- this not work
f : OUT std_logic_vector(7 DOWNTO 0)
);
END multiplier;
Use intermediate signals
library ieee;
use ieee.std_logic_1164.all;
entity multiplier IS
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(3 downto 0);
r : out std_logic_vector(3 downto 0);
f : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of multiplier is
use ieee.numeric_std.all;
signal q_temp: unsigned(3 downto 0) := "0001"; -- or signed
signal r_temp: unsigned(3 downto 0) := "0001"; -- or signed
begin
[...your code...]
q <= std_logic_vector(q_temp);
r <= std_logic_vector(r_temp);
end architecture;

VHDL writing warning

1.8-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M8 is
Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end M8;
architecture Behavioral of M8 is
begin
process(M1,M2)
variable A1: std_logic_vector(17 downto 0);
begin
A1(17 downto 0) := "0000000000" & M1(7 downto 0);
for N in 1 to 9 loop
if A1(0)='1' then
A1(17 downto 9) := A1(17 downto 9) + '0'+ M2(7 downto 0);
end if;
A1(17 downto 0) := '0' & A1(17 downto 1);
end loop;
Mout<= A1(15 downto 0);
end process;
end Behavioral;
2.32-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
Port ( M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0)
);
end M32;
architecture Behavioral of M32 is
begin
process(M1,M2)
variable A1: std_logic_vector(65 downto 0);
begin
A1(65 downto 0) := "0000000000000000000000000000000000" & M1(31 downto 0);
for N in 1 to 33 loop
if A1(0)='1' then
A1(65 downto 33) := A1(65 downto 33) + '0'+ M2(31 downto 0);
end if;
A1(65 downto 0) := '0' & A1(65 downto 1);
end loop;
Mout<= A1(63 downto 0);
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MM32All is
port( MMM1: in std_logic_vector(31 downto 0);
MMM2: in std_logic_vector(31 downto 0);
MMMout: out std_logic_vector(63 downto 0)
);
end MM32All;
architecture Behavioral of MM32All is
component M32 port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end component;
signal MMb: std_logic_vector(31 downto 0);
signal MMa: std_logic_vector(31 downto 0);
signal MMo1: std_logic_vector(39 downto 0);
signal MMo2: std_logic_vector(39 downto 0);
signal MMo3: std_logic_vector(39 downto 0);
signal MMo4: std_logic_vector(39 downto 0);
signal MMout1: std_logic_vector(63 downto 0);
begin
Ma4: M32 port map (MM1=> MMb, MM2=> MMa(31 downto 24), MMout=> MMo4);
Ma3: M32 port map (MM1=> MMb, MM2=> MMa(23 downto 16), MMout=> MMo3);
Ma2: M32 port map (MM1=> MMb, MM2=> MMa(15 downto 8) , MMout=> MMo2);
Ma1: M32 port map (MM1=> MMb, MM2=> MMa(7 downto 0 ) , MMout=> MMo1);
MMout1 <= ("000000000000000000000000" & MMo1) + ("0000000000000000" & MMo2 & "00000000")
+ ("00000000" & MMo3 & "0000000000000000" ) + ( MMo4 & "000000000000000000000000" );
MMb <= MMM1;
MMa <= MMM2;
MMMout <= MMout1;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end M32;
architecture Behavioral of M32 is
component M8 Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8b Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8c Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8d Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
signal internalMM1: std_logic_vector(31 downto 0);
signal internalMM2: std_logic_vector(7 downto 0);
signal internalMMout: std_logic_vector(39 downto 0);
signal M8dout:std_logic_vector(15 downto 0);
signal M8cout:std_logic_vector(15 downto 0);
signal M8bout:std_logic_vector(15 downto 0);
signal M8out:std_logic_vector(15 downto 0);
begin
--addres: for N in 0 to 3 generate
FulMd32: M8d port map( M1=> internalMM1(31 downto 24), M2=> internalMM2, Mout=> M8dout);
FulMb32: M8b port map( M1=> internalMM1(23 downto 16), M2=> internalMM2, Mout=> M8cout);
FulMc32: M8c port map( M1=> internalMM1(15 downto 8), M2=> internalMM2, Mout=> M8bout);
FulM32: M8 port map( M1=> internalMM1(7 downto 0), M2=> internalMM2, Mout=> M8out);
internalMMout<=("000000000000000000000000" & M8out)
+ ("0000000000000000" & M8bout & "00000000") + ("00000000" & M8cout & "0000000000000000")
+ (M8dout & "000000000000000000000000");
internalMM1 <= MM1;
internalMM2 <= MM2;
MMout <= internalMMout;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
port( A :in std_logic_vector(31 downto 0);
B :in std_logic_vector(31 downto 0);
SS:in std_logic_vector(2 downto 0);
C :out std_logic_vector(63 downto 0);
D :out std_logic_vector(31 downto 0);
La,Sm,Eq: out std_logic);
end ALU;
architecture Behavioral of ALU is
Component M32 is port (M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0));
end component;
Component SUB32 is port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
OFL:out std_logic;
S : out STD_LOGIC_vector(31 downto 0));
end component;
Component adder32 is Port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC_vector(31 downto 0));
end component;
signal aM1,aM2,bM1,bM2,cM1,cM2,cMout,bMout : STD_LOGIC_vector(31 downto 0);
signal aMout: STD_LOGIC_vector(63 downto 0);
signal Overflow: std_logic;
begin
A1: M32 port map( M1=> aM1, M2=>aM2, Mout=>aMout);
A2: SUB32 port map(A=> bM1, B=> bM2, S=>bMout, OFL=>Overflow);
A3: adder32 port map(A=> cM1, B=> cM2, Cout=>open,S=>cMout,Cin=>'0');
process(SS,A,B,Overflow,aMout,bMout,CMout)
begin
Case SS is
When "000"=> aM1<=A;
aM2<=B;
C<=aMout;
When "001" => if Overflow='1' then
bM1<=A;
bM2<=B;
D<=bMout;
else
D<="00000000000000000000000000000000";
end if;
when "010" => cM1<=A;
cM2<=B;
D<= cMout;
when "011" => if (A > B) then
La<='1';
Sm<='0';
Eq<='0';
else if (A<B) then
La<='0';
Sm<='1';
Eq<='0';
else
La<='0';
Sm<='0';
Eq<='1';
end if;
end if;
when "100" =>
D <= (A and B);
when "101" =>
D <= (A or B);
when "110" =>
D <= (A xor B);
When others=> C<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
D<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end case;
end process;
end Behavioral;
32-bit ALU
Based on the Device utilization summary, two designs of multiplier have very similar area utilization. 32-bit multiplier by 8-bit multiplier use about 5% more logic unit than single 32-bit multiplier. The number of used route thru used for 32-bit multiplier by 8-bit multiplier is 238% of single 32-bit multiplier. Even use different design, their performance are the same.
You have very obscure way of doing multiplier as scary_jeff indicates. Most likely the synthesis tool gets confused about that.
Instead of
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Please have
use ieee.numeric_std.all;
and instead of
std_logic_vector(n-1 downto 0)
use
signed(n-1 downto 0);
Then you can just multiply with *.
Off topic, but instead of
D<="00000000000000000000000000000000";
you can use
D <= (others => '0');

error in a vhdl code

i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting
the line nos are bold ones in the code here.they are the portmap ones
Can anyone please help me out with this. it would be very kind of you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation: in std_logic_vector(2 downto 0);
Startt : in std_logic;
Ready : out std_logic;
Result_High : out std_logic_vector(3 downto 0);
Result_Low : out std_logic_vector(7 downto 0);
Errorsig : out std_logic;
Reset_n : in std_logic;
Clkk : in std_logic);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
-- And gate
component AND_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- OR Gate
component OR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate
component XOR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- Adder
COMPONENT adder4
PORT
(
C : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
C_out : OUT std_logic);
END COMPONENT;
-- Subtractor
COMPONENT Substractor4
PORT
(
br_in : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
E : out std_logic);
END COMPONENT;
-- Multiplier
COMPONENT mult4by4
port(operA, operB: in std_logic_vector(3 downto 0);
sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;
-- Division
COMPONENT Division
Port ( Dividend : in std_logic_vector(3 downto 0);
Divisor : in std_logic_vector(3 downto 0);
Start : in std_logic;
Clk : in std_logic;
Quotient : out std_logic_vector(3 downto 0);
Remainder : out std_logic_vector(3 downto 0);
Finish : out std_logic);
END COMPONENT;
begin
process(OperandA, OperandB, Startt, Operation) is
begin
case Operation is
when "000" =>
Result_High <= "XXXX";
when "001" =>
Result_High <= OperandA and OperandB;
when "010" =>
Result_High <= OperandA or OperandB;
when "011" =>
Result_High <= OperandA xor OperandB;
when "100" =>
-- Adder
**U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**
when "101" =>
-- Substractor & Error signal
**U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**
when "110" =>
-- multiplication
**U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**
when "111" =>
-- Division
if (OperandB ="0000") then
Errorsig <= '1';
else
**U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
end if;
when others =>
Errorsig <= '1';
end case;
end process;
end architecture Behavioral;
You cannot instantiate entities within a process.
Move all entity instantiations out of the process (into the architecture body) and work from there.
If you want to in instantiate component depending on the value of 'Operation', like the zennehoy wrote, you should instantiate components out of the process and in this case statement only use signal connected to this components in instantiations and link it to port you want.
For the length issue change the "Remainder : out std_logic_vector(3 downto 0);"
to "Remainder : out std_logic_vector(7 downto 0);"

Resources