VHDL TB for 3 bit bcd to binary - vhdl

I've got a problem with my test bench for 3 bit BCD to binary decoder.
Inputs are fine but output is UUUUUU.....
No idea how to resolve it. Should I assign output somehow?
I'm using ISE to simulate code.
I have been trying to apply method I have been using in behavioral model but its not accepting it.
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT bcd_2_bin
PORT(
bcd_in_0 : IN std_logic_vector(3 downto 0);
bcd_in_10 : IN std_logic_vector(3 downto 0);
bcd_in_100 : IN std_logic_vector(3 downto 0);
bin_out : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
signal bcd_in_0 : std_logic_vector(3 downto 0) := (others => '0');
signal bcd_in_10 : std_logic_vector(3 downto 0) := (others => '0');
signal bcd_in_100 : std_logic_vector(3 downto 0) := (others => '0');
signal bin_out : std_logic_vector(9 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_2_bin PORT MAP (
bcd_in_0 => bcd_in_0,
bcd_in_10 => bcd_in_10,
bcd_in_100 => bcd_in_100,
bin_out => bin_out
);
-- Stimulus process
stim_proc: process
begin
bcd_in_0 <= x"0"; bcd_in_10 <= x"1"; bcd_in_100 <= x"2";
wait for 100 ns;
bcd_in_0 <= x"9"; bcd_in_10 <= x"9"; bcd_in_100 <= x"9";
wait for 100 ns;
bcd_in_0 <= x"8"; bcd_in_10 <= x"2"; bcd_in_100 <= x"4";
wait;
end process;
END;

There is no problem in your testbench. I checked with the following dummy UUT,
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bcd_2_bin is
port (
bcd_in_0 : IN std_logic_vector(3 downto 0);
bcd_in_10 : IN std_logic_vector(3 downto 0);
bcd_in_100 : IN std_logic_vector(3 downto 0);
bin_out : OUT std_logic_vector(9 downto 0)
);
end bcd_2_bin;
architecture dummy of bcd_2_bin is
begin
bin_out(3 downto 0) <= bcd_in_0;
bin_out(7 downto 4) <= bcd_in_10;
bin_out(9 downto 8) <= bcd_in_100(1 downto 0);
end dummy;
and simulated your testbench successfully without any changes.
Look inside your UUT source to find the problem. Check also for errors or warnings during compilation.

Related

VHDL-can't add numbers?

Hello I want to build a clock on my ALTERA DE2 that I can adjust the length of by pressing keys.
Now the problem is that when I convert from STD_LOGIC_VECTOR to UNSIGNED the code does not work:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all; Do not use with numeric_std
entity Adjust_Clock_4_buttens is
port(
clk,clk1 : in STD_LOGIC;
minutes_plus, minutes_minus,houres_plus,houres_minus : in STD_LOGIC;
minutes : IN STD_LOGIC_VECTOR(5 downto 0);
houres : IN STD_LOGIC_VECTOR(4 downto 0);
output_minutes : out STD_LOGIC_VECTOR(5 downto 0);
output_houres : out STD_LOGIC_VECTOR(4 downto 0);
LED_0 : OUT STD_LOGIC;
LED_1 : OUT STD_LOGIC;
LED_2 : OUT STD_LOGIC;
LED_3 : OUT STD_LOGIC
);
end entity Adjust_Clock_4_buttens ;
architecture behavioral of Adjust_Clock_4_buttens is
signal button1_r : std_logic_vector(2 downto 0);
signal button2_r : std_logic_vector(2 downto 0);
signal button3_r : std_logic_vector(2 downto 0);
signal button4_r : std_logic_vector(2 downto 0);
-- signal minutes_total : unsigned(5 downto 0) := (others => '0');
-- signal houres_total : unsigned(4 downto 0) := (others => '0');
signal minutes_total : unsigned(5 downto 0);
signal houres_total : unsigned(4 downto 0);
begin
process(clk)
begin
if (rising_edge(clk) )then
minutes_total<=unsigned(minutes);
houres_total<=unsigned(houres);
-- Shift the value of button in button_r
-- The LSB is unused and is there solely for metastability
button1_r <= button1_r(button1_r'left-1 downto 0) & minutes_plus;
button2_r <= button2_r(button2_r'left-1 downto 0) & minutes_minus;
button3_r <= button3_r(button3_r'left-1 downto 0) & houres_plus;
button4_r <= button4_r(button4_r'left-1 downto 0) & houres_minus;
if button1_r(button1_r'left downto button1_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
minutes_total <= (minutes_total + 1);
LED_0<='1';LED_1<='0';LED_2<='0';LED_3<='0';
elsif button2_r(button2_r'left downto button2_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
minutes_total <= (minutes_total-1 );
LED_0<='0';LED_1<='1';LED_2<='0';LED_3<='0';
end if;
if button3_r(button3_r'left downto button3_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
houres_total <= (houres_total + 1);
LED_0<='0';LED_1<='0';LED_2<='1';LED_3<='0';
elsif button4_r(button4_r'left downto button4_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
houres_total<= (houres_total-1 );
LED_0<='0';LED_1<='0';LED_2<='0';LED_3<='1';
end if;
end if;
end process;
output_minutes <= std_logic_vector(minutes_total);
output_houres <= std_logic_vector(houres_total);
end architecture behavioral ;
So in this code I get the time from another block the problem start when I try to add minutes and hours and for some reason it does not react to pressing of the keys. Could anyone explain maybe why is that?
The problem might be that you only have the clock in the sensitivity list of your process. Try adding the buttons in the sensitivity list, since they drive your if conditions. (Not sure if that's the problem but I guess it's worth a try)
minutes_total<=unsigned(minutes);
is on 2 lines, inside and outside of the process, which generates multiple line drivers, and will not work, ever!
(didn't read the rest of the code, there may be other problems, like hours not taking an e)
Now that it's inside the process, you need to rename minutes_total as minute_source, else you're incrementing the value only for the one clock cycle when you have a button edge!

How to initialize a VHDL std_logic_vector to "0001"

i want to initialize my vectors from "0001" instead of "0000" default cause i'm doing an "automatic" 4 Bit multiplier and (x * 0) isn't useful, so
I want to skip the "0000" value.
Here is my Entity:
ENTITY multiplier IS
PORT (
clk, rst : IN std_logic;
q, r : INOUT std_logic_vector (3 DOWNTO 0) := "0001"; -- this not work
f : OUT std_logic_vector(7 DOWNTO 0)
);
END multiplier;
Use intermediate signals
library ieee;
use ieee.std_logic_1164.all;
entity multiplier IS
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(3 downto 0);
r : out std_logic_vector(3 downto 0);
f : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of multiplier is
use ieee.numeric_std.all;
signal q_temp: unsigned(3 downto 0) := "0001"; -- or signed
signal r_temp: unsigned(3 downto 0) := "0001"; -- or signed
begin
[...your code...]
q <= std_logic_vector(q_temp);
r <= std_logic_vector(r_temp);
end architecture;

VHDL Testbench simulation only show three clk cycle

THis is the vhdl code for a fir filter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FIR is
port(
CLK2: in std_logic;
Sendin : in std_logic;
Sendout: out std_logic;
Din : in std_logic_vector(11 downto 0);
Dout: out std_logic_vector(11 downto 0)
);
end FIR;
architecture Behavioral of FIR is
signal count : std_logic_vector(5 downto 0) := "000000";
signal send : std_logic := '0';
signal Dout_S : std_logic_vector(11 downto 0) := x"000";
type multype is array(36 downto 0) of std_logic_vector(23 downto 0);
signal mult : multype := ((others=> (others=>'0')));
type addtype is array(36 downto 0) of std_logic_vector(11 downto 0);
signal adder : addtype :=((others=> (others=>'0')));
type reg is array(36 downto 0) of std_logic_vector(11 downto 0);
signal shiftreg : reg:= ((others=> (others=>'0')));
signal coefs : reg:= (
x"015",x"02F",x"05E",x"0A8",x"114",x"1A8",x"268",x"356",x"472"
,x"5B6",x"71B",x"894",x"A10",x"B7E",x"CCC",x"DE6",x"EBD",x"F43"
,x"F71",x"F43",x"EBD",x"DE6",x"CCC",x"B7E",x"A10",x"894",x"71B"
,x"5B6",x"472",x"356",x"268",x"1A8",x"114",x"0A8",x"05E",x"02F"
,x"015"
);
begin
FIRcal:process(ClK2,Sendin)
begin
if rising_edge(clk2) then
count<=count + 1;
if Sendin = '1' then
shiftreg<=shiftreg(35 downto 0) & Din;
for I in 36 downto 0 loop
MULT(I) <= shiftreg(36-I) * COEFS(36-I);
if I = 0 then
ADDER(I) <= x"000" + ("000000" & MULT(I)(23 downto 17));
else
ADDER(I) <= ("000000" & MULT(I)(23 downto 17)) + ADDER(I-1);
end if;
end loop;
DOUT_S <= ADDER(36);
send <='1';
end if;
end if;
end process FIRcal;
--FIRsend: process(ClK2,Send)
--begin
--if rising_edge(clk2) then
--if send <= '1' then
-- send <='0';
--end if;
--end if;
--end process FIRsend;
Sendout <= Send;
Dout <= Dout_S;
end Behavioral;
Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fvfv IS
END fvfv;
ARCHITECTURE behavior OF fvfv IS
COMPONENT FIR
PORT(
CLK2 : IN std_logic;
Sendin : IN std_logic;
Sendout : OUT std_logic;
Din : IN std_logic_vector(11 downto 0);
Dout : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
--Inputs
signal CLK2 : std_logic := '0';
signal Sendin : std_logic := '0';
signal Din : std_logic_vector(11 downto 0) := (others => '0');
--Outputs
signal Sendout : std_logic;
signal Dout : std_logic_vector(11 downto 0);
-- Clock period definitions
constant CLK2_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FIR PORT MAP (
CLK2 => CLK2,
Sendin => Sendin,
Sendout => Sendout,
Din => Din,
Dout => Dout
);
-- Clock process definitions
CLK2_process :process
begin
CLK2 <= '0';
wait for CLK2_period/2;
CLK2 <= '1';
wait for CLK2_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Din <= x"0F0";
wait for 10 ns;
sendin<='1';
wait for 10 ns;
sendin<='0';
wait for 300 ns;
Din <= x"090";
sendin<='1';
wait for 10 ns;
sendin<='0';
end process;
END;
enter image description here
enter image description here
The testbench only show three clk cycles, I try to extend the time, but it didn't work, Is there any problem for my Code?
You have an error in follow lines:
if I = 0 then
ADDER(I) <= x"000" + ("00000" & MULT(I)(23 downto 17));
else
ADDER(I) <= ("00000" & MULT(I)(23 downto 17)) + ADDER(I-1);
end if;
As I told in comments you have different sizes of vectors.
To solve the issue you need to equate the sizes in depends on your logic (remove one 0 from right side or expand ADDER elements:
if I = 0 then
ADDER(I) <= x"000" + ("0000" & MULT(I)(23 downto 17));
else
ADDER(I) <= ("0000" & MULT(I)(23 downto 17)) + ADDER(I-1);
end if;
OR
type addtype is array(36 downto 0) of std_logic_vector(12 downto 0);
signal adder : addtype :=((others=> (others=>'0')));

Can't get VHDL Sequential Multiplier to Multiply correctly

I have a School Lab that I must do pertaining to creating a sequential multiplier in VHDL. My issues is happening before making the finite state machine for the sequential multiplier. I can not get the base model to multiply correctly, I think I have a issue in my test bench but am not 100% sure of this. I still have doubt that the issue is in my code.
Top Design (basically calling the D-Flip-Flops, MUX and Adder)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity toplvds is
port( A,B: in std_logic_vector(3 downto 0);
Zero: in std_logic_vector(3 downto 0);
clk, clr, load, loadP, sb: in std_logic;
Po: out std_logic_vector(7 downto 0));
end toplvds;
architecture Behavioral of toplvds is
component dffa
port( dina: in std_logic_vector(3 downto 0);
clr, clk, load: in std_logic;
q: out std_logic_vector(3 downto 0));
end component;
component dffb
port( dinb: in std_logic_vector(3 downto 0);
clr, clk, load, sb: in std_logic;
qb0: out std_logic);
end component;
component mux
port( d0,d1: in std_logic_vector(3 downto 0);
s: in std_logic;
y: out std_logic_vector(3 downto 0));
end component;
component adder
port( a,b: in std_logic_vector(3 downto 0);
cry: out std_logic;
r: out std_logic_vector(3 downto 0));
end component;
component dffP
port( dinp: in std_logic_vector(3 downto 0);
carry: in std_logic;
clr, clk, loadP, sb: in std_logic;
PHout: out std_logic_vector (3 downto 0);
P: out std_logic_vector(7 downto 0));
end component;
signal Wire1: std_logic_vector(3 downto 0);
signal Wire2: std_logic_vector(3 downto 0);
signal Wire3: std_logic;
signal Wire4: std_logic_vector(3 downto 0);
signal Wire5: std_logic_vector(3 downto 0);
signal Wire6: std_logic_vector(3 downto 0);
signal Wire7: std_logic;
begin
Wire1 <= Zero;
u1: dffa port map (dina=>A,clr=>clr,clk=>clk,load=>load,q=>Wire2);
u2: dffb port map (dinb=>B,clr=>clr,clk=>clk,load=>load,sb=>sb,qb0=>Wire3);
u3: mux port map (d0=>Wire2,d1=>Wire1,s=>Wire3,y=>Wire4);
u4: adder port map (a=>Wire6,b=>Wire4,cry=>Wire7,r=>Wire5);
u5: dffp port map (dinp=>Wire5,carry=>Wire7,clr=>clr,clk=>clk,loadP=>loadP,sb=>sb,PHout=>Wire6,P=>Po);
end Behavioral;
D-Flip-Flop for Multiplicand
library ieee;
use ieee.std_logic_1164.all;
entity dffa is
port( dina: in std_logic_vector(3 downto 0);
clr, clk, load: in std_logic;
q: out std_logic_vector(3 downto 0));
end dffa;
architecture beh of dffa is
begin
process(clk,clr)
begin
if(clr = '1') then
q <= ( others => '0');
elsif (rising_edge(clk)) then
if(load = '1') then
q <= dina;
end if;
end if;
end process;
end beh;
D-Flip-Flop for Multiplier
library ieee;
use ieee.std_logic_1164.all;
entity dffb is
port( dinb: in std_logic_vector(3 downto 0);
clr, clk, load, sb: in std_logic;
qb0: out std_logic);
end dffb;
architecture beh of dffb is
signal q: std_logic_vector(3 downto 0);
begin
qb0 <= q(0);
process(clk,clr, load, sb)
begin
if(clr = '1') then
q <= ( others => '0');
elsif (rising_edge(clk)) then
if(load = '1') then
q <= dinb;
elsif (sb = '1') then
q <= '0' & q ( 3 downto 1);
end if;
end if;
end process;
end beh;
MUX
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port( d0,d1: in std_logic_vector(3 downto 0);
s: in std_logic;
y: out std_logic_vector(3 downto 0));
end mux;
architecture beh of mux is
begin
y <= d0 when s = '1' else d1;
end beh;
Adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity adder is
port( a,b: in std_logic_vector(3 downto 0);
cry: out std_logic;
r: out std_logic_vector(3 downto 0));
end adder;
architecture beh of adder is
signal temp : std_logic_vector(4 downto 0);
begin
temp <= ('0' & a) + ('0' & b);
r <= temp(3 downto 0);
cry <= temp(4);
end beh;
D-Flip-Flop for Product
library ieee;
use ieee.std_logic_1164.all;
entity dffp is
port( dinp: in std_logic_vector(3 downto 0);
carry: in std_logic;
clr, clk, loadP, sb: in std_logic;
PHout: out std_logic_vector (3 downto 0);
P: out std_logic_vector(7 downto 0));
end dffp;
architecture beh of dffp is
signal q: std_logic_vector(7 downto 0);
begin
--qp0 <= q(0);
process(clk,clr, loadP, sb)
begin
if(clr = '1') then
q <= ( others => '0');
elsif (rising_edge(clk)) then
if(loadP = '1') then
--q <= "00000000";
q(7 downto 4) <= dinp;
elsif (sb = '1') then
q <= carry & q ( 7 downto 1);
--else
--q(7 downto 4) <= dinp;
end if;
end if;
end process;
PHout <= q(7 downto 4);
P <= q;
end beh;
TEST-BENCH Code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY toplvds_tb IS
END toplvds_tb;
ARCHITECTURE behavior OF toplvds_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplvds
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Zero : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
clr : IN std_logic;
load : IN std_logic;
loadP : IN std_logic;
sb : IN std_logic;
Po : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Zero : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal clr : std_logic := '0';
signal load : std_logic := '0';
signal loadP : std_logic := '0';
signal sb : std_logic := '0';
--Outputs
signal Po : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplvds PORT MAP (
A => A,
B => B,
Zero => Zero,
clk => clk,
clr => clr,
load => load,
loadP => loadP,
sb => sb,
Po => Po
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
A <= "1011";
B <= "1101";
Zero <="0000";
load <= '0';
sb <= '0';
clr <= '1';
wait for 12 ns;
clr <= '0'; load <= '1';
wait for 12 ns;
load <= '0'; sb <= '1';
wait for 12 ns;
sb <= '0'; loadP <= '1';
wait for 12 ns;
loadP <= '0'; sb <= '1';
wait for 12 ns;
sb <= '0'; loadP <= '1';
wait for 12 ns;
loadP <= '0'; sb <= '1';
wait for 12 ns;
sb <= '0'; loadP <= '1';
wait for 12 ns;
loadP <= '0'; sb <= '1';
wait for 12 ns;
sb <= '0'; loadP <= '1';
wait for 12 ns;
loadP <= '0'; sb <= '1';
wait for 20 ns;
loadP <= '0'; sb <= '0';
wait;
end process;
END;
Sorry that I have not commented the code for better understanding. I know this will be hard to follow but I hope someone will. I will also attach an image of the figure of the sequential multiplier I am following, the circuit design.
4 by 4 binary sequential multiplier circuit
4 by 4 binary sequential multiplier circuit - more
Well it was indeed something in the testbench that was giving issues. I worked it out in the lab with fellow classmates. Thank You for your help anyways it is much appreciated.
p.s. All I did was changed some timing values in the testbench at the very bottom to when the load and shift bit would happen and I got it to work.

VHDL : Value not propagating to port map

I have the below VHDL file, where i am facing problem. The final sum is getting the value undefined always.
CL_Adder is the Carry lookahead adder and is check as individual component and is working fine. Regstr module is also working fine.
The problem is with the reslt, reslt_out1, reslt_out2 variables usage ..!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CS_Adder_Package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity movingaverage is
Port ( sin : in STD_LOGIC_VECTOR (10 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--reslt_in: in std_logic_vector(14 downto 0);
sout : out STD_LOGIC_VECTOR (10 downto 0)
--reslt_out: out std_logic_vector(14 downto 0)
);
end movingaverage;
architecture Structural of movingaverage is
component Regstr is
port ( d : in STD_LOGIC_VECTOR (10 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (10 downto 0));
end component;
component CL_Adder is
Port ( x : in STD_LOGIC_VECTOR (14 downto 0);
y : in STD_LOGIC_VECTOR (14 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (14 downto 0);
cout : out STD_LOGIC);
end component;
signal s: input_array;
signal s_se :std_logic_vector(14 downto 0):= (others =>'0');
signal s_se1 :std_logic_vector(14 downto 0):= (others =>'0');
signal s_se2 : std_logic_vector(14 downto 0):= (others =>'0');
signal reslt : std_logic_vector(14 downto 0):= (others =>'0');
signal reslt_out1: std_logic_vector(14 downto 0):= (others =>'0');
signal reslt_out2: std_logic_vector(14 downto 0):= (others =>'0');
signal c1,c2: std_logic;
begin
u0: for i in 15 downto 1 generate
u1:regstr port map(s(i-1)(10 downto 0),clk,rst,s(i)(10 downto 0));
end generate u0;
u7:regstr port map(sin,clk,rst,s(0)(10 downto 0));
s_se(14 downto 0) <= sin(10) & sin(10) & sin(10) & sin(10) & sin(10 downto 0);
reslt<= reslt_out2;
u8:CL_Adder port map(s_se,reslt,'0',reslt_out1,c1);
s_se1<= s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10 downto 0);
s_se2 <= not(s_se1);
u9:CL_Adder port map(reslt_out1,s_se2,'1',reslt_out2,c2);
Sout <= reslt(14 downto 4); --divide by 16
end Structural;
Without more code I must add a little guessing, but could look like there is a
loop in the design in reslt => reslt_out1 => reslt_out2 => reslt, since
there is no clock (clk) on CL_Adder in the code:
reslt <= reslt_out2;
...
u8:CL_Adder port map(s_se, reslt, '0', reslt_out1, c1);
...
u9:CL_Adder port map(reslt_out1, s_se2, '1', reslt_out2, c2);
Whether this is the reason for the problem depends on how you see the
"undefined". In simulation the loop itself should not result in X (unknown),
or similar, but the loop hints a problem. Btw, you mention "variables usage",
but there are no variables in the shown code; only signals.
Addition:
If the purpose is to accumulate the value, then a sequential process (clocked process to make flip flops) may be used to capture the result of each iteration, and present as argument in next iteration. The reslt <= reslt_out2; may then be replaced with a process like:
process (clk, rst) is
begin
if rst = '1' then -- Reset if required
reslt <= (others => '0');
elsif rising_edge(clk) then -- Clock
reslt <= reslt_out2;
end if;
end process;

Resources