i want to initialize my vectors from "0001" instead of "0000" default cause i'm doing an "automatic" 4 Bit multiplier and (x * 0) isn't useful, so
I want to skip the "0000" value.
Here is my Entity:
ENTITY multiplier IS
PORT (
clk, rst : IN std_logic;
q, r : INOUT std_logic_vector (3 DOWNTO 0) := "0001"; -- this not work
f : OUT std_logic_vector(7 DOWNTO 0)
);
END multiplier;
Use intermediate signals
library ieee;
use ieee.std_logic_1164.all;
entity multiplier IS
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(3 downto 0);
r : out std_logic_vector(3 downto 0);
f : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of multiplier is
use ieee.numeric_std.all;
signal q_temp: unsigned(3 downto 0) := "0001"; -- or signed
signal r_temp: unsigned(3 downto 0) := "0001"; -- or signed
begin
[...your code...]
q <= std_logic_vector(q_temp);
r <= std_logic_vector(r_temp);
end architecture;
Related
Thank you, everyone, here I have modified the post. I have written a simple code VHDL for trap filter by using different components for each task. The below is sample code where different components are used and all the other components are working perfectly except accumulator component(acc1), the out signal remains zero. In the acc1 one component I am trying to to make two accumulators where the first acc1 (output of the first accumulator) is the input for the acc2. As the other components are working so here I only showed the port mapping of acc1 component in the code along the test bench.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use ieee.fixed_pkg.all;
ENTITY TRAPFILTER IS
GENERIC (
K : integer :=80;
L : integer :=200
--M : signed(9 downto 0) := to_signed(5)
);
PORT
(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DATAOUT : OUT STD_LOGIC_VECTOR(24 DOWNTO 0);
DATAOUT1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); ---
READY : OUT STD_LOGIC;
Soutout : out std_logic_vector(23 downto 0);
Koutout : out std_logic_vector(13 downto 0);
Loutout : out std_logic_vector(13 downto 0)
);
END ENTITY TRAPFILTER;
ARCHITECTURE RTL OF TRAPFILTER IS
constant M : sfixed(1 downto -2) := to_sfixed(0.01,1,-2);
type Sdelay_reg is array(0 to 2) OF signed(21 downto 0);
signal S_reg : Sdelay_reg :=(others=>(others=>'0'));
-------------------------------------------------------------
signal y_reg0 : signed (27 downto 0) :=(others=>'0');
signal y_reg1 : signed (31 downto 0) :=(others=>'0');
-----------------------------------------------------------
signal in_reg : signed(13 downto 0) :=(others=>'0');
signal out_reg : signed(DATAOUT'length-1 downto 0) :=
(others=>'0');
-- ----------------------------------------------------------
signal fs : std_logic :='0';
--------------------kdelay component----------------------------------
component kdelay is
GENERIC (
K : integer :=80;
L : integer :=200
);
port
(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto 0);
kout : OUT STD_LOGIC_VECTOR (13 downto 0)
);
end component;
signal kout : std_logic_vector (13 downto 0) :=(others=>
'0');
--------------------Ldelay component----------------------
------------
component Ldelay is
GENERIC (
K : integer :=80;
L : integer :=200
);
port
(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto
0);
Lout : OUT STD_LOGIC_VECTOR (13 downto
0)
);
end component;
signal Lout : std_logic_vector (13 downto 0) :=
(others=>'0');
---------------------------------------------------
component sub_mult is
port(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (13 downto
0);
Sout : out STD_LOGIC_VECTOR (23
downto 0)
);
end component;
signal Sout : std_logic_vector (23
downto 0) :=(others=>'0');
-------------------------------------------
component accum1 is
port(
clk : in std_logic ;
rst : in std_logic;
din : in
STD_LOGIC_VECTOR (23 downto 0);
Acout : out
STD_LOGIC_VECTOR (24 downto 0);
Acout1 : out
STD_LOGIC_VECTOR (25 downto 0)
);
end component;
signal acc_out1 : std_logic_vector (24 downto 0) :=(others=>'0');
signal acc_out2 : std_logic_vector (25 downto 0) :=(others=>'0');
----------------------------------------------------------------
BEGIN
Koutout <= Kout;
Loutout <= Lout;
Soutout <= Sout;
in_reg <= signed (DATAIN);
DATAOUT <= acc_out1;--std_logic_vector(out_reg);
DATAOUT1 <= acc_out2;
utacc1:component accum1
port map(
clk => clk,
rst => rst,--: in std_logic;
din => Sout, --: OUT STD_LOGIC_VECTOR
(13 downto 0);
Acout => acc_out1, -- : out STD_LOGIC_VECTOR (24 downto 0)
Acout1 => acc_out2
);
END RTL;
------------------------Accum1 component----------------------------------
library IEEEieee;`
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use ieee.fixed_pkg.all;
entity accum1 is port(
clk : in std_logic ;
rst : in std_logic;
din : in STD_LOGIC_VECTOR (23 downto 0);
Acout : out STD_LOGIC_VECTOR (24 downto 0);
Acout1 : out STD_LOGIC_VECTOR (25 downto 0)
);
end entity;
architecture rtl of accum1 is
signal dout : signed(24 downto 0) :=(others=>'0');
signal datain : signed(23 downto 0) :=(others=>'0');
signal dout2 : signed(25 downto 0) :=(others=>'0');
begin
datain <= signed(din);
process(clk,rst,datain)
variable cm : signed(24 downto 0);
begin
if(rst='1' ) then
dout <= (others=>'0');
dout2 <= (others=>'0');
cm := (others=>'0');
elsif(rising_edge(clk) and clk'event) then
cm := datain + cm;
dout <= cm ;
dout2 <= dout2 + cm ;
end if;
end process;
Acout <= std_logic_vector(dout);
Acout1 <= std_logic_vector(dout2) ;
end rtl;
------------------------test bench only trapfilter comppnent portmapping
uttrap5:component TRAPFILTER
PORT MAP
(
CLK => TestClk, -- : IN STD_LOGIC;
RST => i_rstb, -- : IN STD_LOGIC;
DATAIN => odata, --odata, -- : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DATAOUT => trap_out, --: OUT STD_LOGIC_VECTOR(13 DOWNTO 0); ---
DATAOUT1 => trap_out1,
READY => trap_ready, --: OUT STD_LOGIC
Koutout => Koutout, --out std_logic_vector(23 downto 0);
Loutout => loutout, --: out std_logic_vector(13 downto 0);
Soutout => Soutout
);
enter image description here
Several issues in your code
You don't need datain in your sensitivity list.
When using rising_edge, you don't need event
The variable cm will not keep their value when re-enter the process. Use signal instead or just use value of dout.
I am really understand what is your dout2 logic?
why does the following code generate the error message "vhdl:warning: universal integer bound must be numeric literal or attribute" on the line: " type mem_type is array ((2**ADDR_WIDTH)-1 downto) of std_logic_vector (DATA_WIDTH-1 downto 0);" and how do I fix it?
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bus_fifo_mem is
generic(
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
ENABLE_BYPASS : integer := 1
);
port(
clk : in std_logic;
raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
re : in std_logic;
waddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
we : in std_logic;
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity;
architecture rtl of bus_fifo_mem is
signal rdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal din_r : std_logic_vector(DATA_WIDTH-1 downto 0);
signal bypass : std_logic;
-- VERILOG
--reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
type mem_type is array ((2**ADDR_WIDTH)-1 downto 0)
of std_logic_vector (DATA_WIDTH-1 downto 0);
signal mem : mem_type := (others => (others => '0'));
begin
process(clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(to_integer(unsigned(waddr))) <= din;
end if;
if (re = '1') then
rdata <= mem(to_integer(unsigned(raddr)));
end if;
end if;
end process;
end architecture;
Use this:
type mem_type is array (integer'(2) ** ADDR_WIDTH - 1 downto 0)
of std_logic_vector(DATA_WIDTH-1 downto 0);
Instead of this:
type mem_type is array ((2**ADDR_WIDTH)-1 downto 0)
of std_logic_vector (DATA_WIDTH-1 downto 0);
Complete working example:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bus_fifo_mem is
generic(
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
ENABLE_BYPASS : integer := 1
);
port(
clk : in std_logic;
raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
re : in std_logic;
waddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
we : in std_logic;
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity;
architecture rtl of bus_fifo_mem is
signal rdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal din_r : std_logic_vector(DATA_WIDTH-1 downto 0);
signal bypass : std_logic;
-- VERILOG
--reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
type mem_type is array (integer'(2) ** ADDR_WIDTH - 1 downto 0)
of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : mem_type := (others => (others => '0'));
begin
process(clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(to_integer(unsigned(waddr))) <= din;
end if;
if (re = '1') then
rdata <= mem(to_integer(unsigned(raddr)));
end if;
end if;
end process;
end architecture;
I'm writing something in VHDL about an essay and I'm facing a strange situation. I've written some components, simulated and tested them, and everything seems to works fine. However, when simulating the top entity, I'm getting zeros as a result! Please take a look at the following listings:
Top Entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity foobar is
port ( data_i : in std_logic_vector(39 downto 0);
sum_12bit_o : out std_logic_vector(11 downto 0)
);
end foobar;
architecture Behavioral of foobar is
--Declare components
component four_10bit_word_adder is
port( --Input signals
a_byte_in: in std_logic_vector(9 downto 0);
b_byte_in: in std_logic_vector(9 downto 0);
c_byte_in: in std_logic_vector(9 downto 0);
d_byte_in: in std_logic_vector(9 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(11 downto 0)
);
end component;
-- Signal declaration
signal int: std_logic_vector(11 downto 0);
signal intdata: std_logic_vector(39 downto 0);
begin
intdata <= data_i; --DEBUG
U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),
intdata(19 downto 10), intdata(9 downto 0),
'0', int);
end Behavioral;
four_10bit_word_adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_10bit_word_adder is
generic (
bits: integer := 10
);
port( --Input signals
a_byte_in: in std_logic_vector(bits-1 downto 0);
b_byte_in: in std_logic_vector(bits-1 downto 0);
c_byte_in: in std_logic_vector(bits-1 downto 0);
d_byte_in: in std_logic_vector(bits-1 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(bits+1 downto 0)
);
end four_10bit_word_adder;
architecture Behavioral of four_10bit_word_adder is
-- Component Declaration
component compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end component;
--------------------------------------------------------+
component generic_11bit_adder
port (
A: in std_logic_vector(10 downto 0); --Input A
B: in std_logic_vector(10 downto 0); --Input B
CI: in std_logic; --Carry in
O: out std_logic_vector(10 downto 0); --Sum
CO: out std_logic --Carry Out
);
end component;
--------------------------------------------------------+
-- Declare internal signals
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal
signal byte_out: std_logic_vector(bits-1 downto 0);
signal carry: std_logic_vector(bits-1 downto 0);
signal int11bit: std_logic_vector(bits downto 0);
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder.
-- See the paper for more info.
signal Concat_A: std_logic_vector(bits downto 0);
signal Concat_B: std_logic_vector(bits downto 0);
signal co : std_logic;
begin
A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),
c_byte_in(0), d_byte_in(0),
'0', int(0), byte_out(0), carry(0));
instances: for i in 1 to bits-1 generate
A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),
c_byte_in(i), d_byte_in(i), int(i-1),
int(i), byte_out(i), carry(i));
end generate;
R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co);
Concat_A <= int(8) & byte_out;
Concat_B <= carry & '0';
process (co)
begin
if (co = '1') then
val12bit_out <= '1' & int11bit;
else
val12bit_out <= '0' & int11bit;
end if;
end process;
end Behavioral;
4:2 Compressor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end compressor_4_2;
architecture Behavioral of compressor_4_2 is
-- Internal Signal Definitions
signal stage_1: std_logic;
begin
stage_1 <= d XOR (b XOR c);
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d));
sum <= (a XOR cin) XOR stage_1;
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1));
end Behavioral;
Generic 11-bit Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic_11bit_adder is
generic (
bits: integer := 11
);
port (
A: in std_logic_vector(bits-1 downto 0);
B: in std_logic_vector(bits-1 downto 0);
CI: in std_logic;
O: out std_logic_vector(bits-1 downto 0);
CO: out std_logic
);
end entity generic_11bit_adder;
architecture Behavioral of generic_11bit_adder is
begin
process(A,B,CI)
variable sum: integer;
-- Note: we have one bit more to store carry out value.
variable sum_vector: std_logic_vector(bits downto 0);
begin
-- Compute our integral sum, by converting all operands into integers.
sum := conv_integer(A) + conv_integer(B) + conv_integer(CI);
-- Now, convert back the integral sum into a std_logic_vector, of size bits+1
sum_vector := conv_std_logic_vector(sum, bits+1);
-- Assign outputs
O <= sum_vector(bits-1 downto 0);
CO <= sum_vector(bits); -- Carry is the most significant bit
end process;
end Behavioral;
I've tried a ton of things, but without any success. Do you have any idea what am I doing wrong? Sorry for the long question and thank you for your time.
Take a look at your process to generate val12bit_out in your four_10bit_word_adder entity. It's missing an input.
Also, there are several other issues. Fixing this one issue will not fix everything. But once you fix it, I think things will be a lot more clear.
i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting
the line nos are bold ones in the code here.they are the portmap ones
Can anyone please help me out with this. it would be very kind of you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation: in std_logic_vector(2 downto 0);
Startt : in std_logic;
Ready : out std_logic;
Result_High : out std_logic_vector(3 downto 0);
Result_Low : out std_logic_vector(7 downto 0);
Errorsig : out std_logic;
Reset_n : in std_logic;
Clkk : in std_logic);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
-- And gate
component AND_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- OR Gate
component OR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate
component XOR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- Adder
COMPONENT adder4
PORT
(
C : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
C_out : OUT std_logic);
END COMPONENT;
-- Subtractor
COMPONENT Substractor4
PORT
(
br_in : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
E : out std_logic);
END COMPONENT;
-- Multiplier
COMPONENT mult4by4
port(operA, operB: in std_logic_vector(3 downto 0);
sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;
-- Division
COMPONENT Division
Port ( Dividend : in std_logic_vector(3 downto 0);
Divisor : in std_logic_vector(3 downto 0);
Start : in std_logic;
Clk : in std_logic;
Quotient : out std_logic_vector(3 downto 0);
Remainder : out std_logic_vector(3 downto 0);
Finish : out std_logic);
END COMPONENT;
begin
process(OperandA, OperandB, Startt, Operation) is
begin
case Operation is
when "000" =>
Result_High <= "XXXX";
when "001" =>
Result_High <= OperandA and OperandB;
when "010" =>
Result_High <= OperandA or OperandB;
when "011" =>
Result_High <= OperandA xor OperandB;
when "100" =>
-- Adder
**U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**
when "101" =>
-- Substractor & Error signal
**U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**
when "110" =>
-- multiplication
**U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**
when "111" =>
-- Division
if (OperandB ="0000") then
Errorsig <= '1';
else
**U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
end if;
when others =>
Errorsig <= '1';
end case;
end process;
end architecture Behavioral;
You cannot instantiate entities within a process.
Move all entity instantiations out of the process (into the architecture body) and work from there.
If you want to in instantiate component depending on the value of 'Operation', like the zennehoy wrote, you should instantiate components out of the process and in this case statement only use signal connected to this components in instantiations and link it to port you want.
For the length issue change the "Remainder : out std_logic_vector(3 downto 0);"
to "Remainder : out std_logic_vector(7 downto 0);"
I have the below VHDL file, where i am facing problem. The final sum is getting the value undefined always.
CL_Adder is the Carry lookahead adder and is check as individual component and is working fine. Regstr module is also working fine.
The problem is with the reslt, reslt_out1, reslt_out2 variables usage ..!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CS_Adder_Package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity movingaverage is
Port ( sin : in STD_LOGIC_VECTOR (10 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--reslt_in: in std_logic_vector(14 downto 0);
sout : out STD_LOGIC_VECTOR (10 downto 0)
--reslt_out: out std_logic_vector(14 downto 0)
);
end movingaverage;
architecture Structural of movingaverage is
component Regstr is
port ( d : in STD_LOGIC_VECTOR (10 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (10 downto 0));
end component;
component CL_Adder is
Port ( x : in STD_LOGIC_VECTOR (14 downto 0);
y : in STD_LOGIC_VECTOR (14 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (14 downto 0);
cout : out STD_LOGIC);
end component;
signal s: input_array;
signal s_se :std_logic_vector(14 downto 0):= (others =>'0');
signal s_se1 :std_logic_vector(14 downto 0):= (others =>'0');
signal s_se2 : std_logic_vector(14 downto 0):= (others =>'0');
signal reslt : std_logic_vector(14 downto 0):= (others =>'0');
signal reslt_out1: std_logic_vector(14 downto 0):= (others =>'0');
signal reslt_out2: std_logic_vector(14 downto 0):= (others =>'0');
signal c1,c2: std_logic;
begin
u0: for i in 15 downto 1 generate
u1:regstr port map(s(i-1)(10 downto 0),clk,rst,s(i)(10 downto 0));
end generate u0;
u7:regstr port map(sin,clk,rst,s(0)(10 downto 0));
s_se(14 downto 0) <= sin(10) & sin(10) & sin(10) & sin(10) & sin(10 downto 0);
reslt<= reslt_out2;
u8:CL_Adder port map(s_se,reslt,'0',reslt_out1,c1);
s_se1<= s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10) & s(15)(10 downto 0);
s_se2 <= not(s_se1);
u9:CL_Adder port map(reslt_out1,s_se2,'1',reslt_out2,c2);
Sout <= reslt(14 downto 4); --divide by 16
end Structural;
Without more code I must add a little guessing, but could look like there is a
loop in the design in reslt => reslt_out1 => reslt_out2 => reslt, since
there is no clock (clk) on CL_Adder in the code:
reslt <= reslt_out2;
...
u8:CL_Adder port map(s_se, reslt, '0', reslt_out1, c1);
...
u9:CL_Adder port map(reslt_out1, s_se2, '1', reslt_out2, c2);
Whether this is the reason for the problem depends on how you see the
"undefined". In simulation the loop itself should not result in X (unknown),
or similar, but the loop hints a problem. Btw, you mention "variables usage",
but there are no variables in the shown code; only signals.
Addition:
If the purpose is to accumulate the value, then a sequential process (clocked process to make flip flops) may be used to capture the result of each iteration, and present as argument in next iteration. The reslt <= reslt_out2; may then be replaced with a process like:
process (clk, rst) is
begin
if rst = '1' then -- Reset if required
reslt <= (others => '0');
elsif rising_edge(clk) then -- Clock
reslt <= reslt_out2;
end if;
end process;