I've got multiple (same) input/output to declare :
B1_data_to_send : in std_logic_vector(15 downto 0);
B1_start_transmission : out std_logic;
B1_transmission_busy : in std_logic;
B2_data_to_send : in std_logic_vector(15 downto 0);
B2_start_transmission : out std_logic;
B2_transmission_busy : in std_logic;
B3_data_to_send : in std_logic_vector(15 downto 0);
B3_start_transmission : out std_logic;
B3_transmission_busy : in std_logic;
B4_data_to_send : in std_logic_vector(15 downto 0);
B4_start_transmission : out std_logic;
B4_transmission_busy : in std_logic;
B5_data_to_send : in std_logic_vector(15 downto 0);
B5_start_transmission : out std_logic;
B5_transmission_busy : in std_logic;
B6_data_to_send : in std_logic_vector(15 downto 0);
B6_start_transmission : out std_logic;
B6_transmission_busy : in std_logic;
I've got 30 block like this to create, is there a way to avoid this repetition and to create a generic block that I can instantiate with different names ?
Arrays are what you need here. First, you will need to create an array type of std_logic_vector in a package. If you're using VHDL 2008, it can simply be an unconstrained type:
package types_pkg is
type slv_array_t is array(natural range <>) of std_logic_vector;
end package;
and then use this type in your entity:
use work.types_pkg.all;
entity your_entity is
port (
B_data_to_send : in slv_array_t (1 to 30)(15 downto 0);
B_start_transmission : out std_logic_vector(1 to 30);
B_transmission_busy : in std_logic_vector(1 to 30)
);
end entity;
Of course, any of the dimensions can come from a generic.
use work.types_pkg.all;
entity your_entity is
generic (
G_N_PORTS : natural;
G_D_WIDTH : natural
);
port (
B_data_to_send : in slv_array_t (0 to G_N_PORTS-1)(G_D_WIDTH-1 downto 0);
B_start_transmission : out std_logic_vector(0 to G_N_PORTS-1);
B_transmission_busy : in std_logic_vector(0 to G_N_PORTS-1)
);
end entity;
I'm very new to VHDL and FPGAs, and have hit a rock. Im currently working on video filters on the zybo z7-10, and started off using this guide to create a HDMI passthrough on the board:
https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679
So after getting that working all i want to do is be able to effect the video output. To do this, I tried to set the rgb 24 bit vectors last 8 bits to 0, removing all blue from the output. If i try the following code (with or without the process block) i get a syntax error on the "if" statement line
process is
begin
if sw ='0' then
vid_pData(7 downto 0) <= sw
end if;
end process;
The issue is I don't seem to be able to put this anywhere in the code without causing an error. Can someone explain what's happening here?
Full code below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity hdmi_pass_top is
Port (
sysclk_i : in std_logic; -- 125MH System Clock Input
async_reset_i : in std_logic; -- Reset switch on board
-- HDMI In/Rx
tmds_rx_clk_p_i : in std_logic;
tmds_rx_clk_n_i : in std_logic;
tmds_rx_data_p_i : in std_logic_vector(2 downto 0);
tmds_rx_data_n_i : in std_logic_vector(2 downto 0);
hdmi_rx_hpd_o : out std_logic := '1'; -- HPD must be driven
-- I2C
sda_io : inout std_logic;
scl_io : inout std_logic;
-- HDMI Out/Tx
tmds_tx_clk_p_o : out std_logic;
tmds_tx_clk_n_o : out std_logic;
tmds_tx_data_p_o : out std_logic_vector(2 downto 0);
tmds_tx_data_n_o : out std_logic_vector(2 downto 0);
sw : in std_logic
);
end hdmi_pass_top;
architecture hdmi_pass_top_arc of hdmi_pass_top is
component dvi2rgb_0
port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
RefClk : in std_logic;
aRst : in std_logic;
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic;
aPixelClkLckd : out std_logic;
SDA_I : in std_logic;
SDA_O : out std_logic;
SDA_T : out std_logic;
SCL_I : in std_logic;
SCL_O : out std_logic;
SCL_T : out std_logic;
pRst : in std_logic
);
end component;
component rgb2dvi_0
PORT (
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
aRst : in std_logic;
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic
);
end component;
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal vid_pData : std_logic_vector(23 downto 0);
signal vid_pVDE : std_logic;
signal vid_pHSync : std_logic;
signal vid_pVSync : std_logic;
signal pixelclk : std_logic;
signal locked : std_logic;
signal clk_200M : std_logic;
signal pixel_clk_sync_rst : std_logic;
signal sda_i : std_logic;
signal sda_o : std_logic;
signal sda_t : std_logic;
signal scl_i : std_logic;
signal scl_o : std_logic;
signal scl_t : std_logic;
begin
clkwiz_inst : clk_wiz_0
port map (
-- Clock out ports
clk_out1 => clk_200M,
-- Status and control signals
reset => async_reset_i,
locked => locked,
-- Clock in ports
clk_in1 => sysclk_i
);
dvi2rgb_inst : dvi2rgb_0
port map (
TMDS_Clk_p => tmds_rx_clk_p_i,
TMDS_Clk_n => tmds_rx_clk_n_i,
TMDS_Data_p => tmds_rx_data_p_i,
TMDS_Data_n => tmds_rx_data_n_i,
RefClk => clk_200M,
aRst => async_reset_i, --Active high asynchronous RefClk reset
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk,
aPixelClkLckd => open, --
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
pRst => '0' -- Active high PixelClk synchronous reset
);
SDA_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => sda_i, -- Buffer output
IO => sda_io, -- Buffer inout port(connect directly to top-level port)
I => sda_o, -- Bufferinput
T => sda_t -- 3-state enable input,high=input,low=output
);
SCL_IOBUF_inst: IOBUF
generic map(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map(
O => scl_i, -- Buffer output
IO => scl_io, -- Buffer inout port(connect directly to top-level port)
I => scl_o, -- Buffer input
T => scl_t -- 3-state enable input,high=input,low=output
);
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
end hdmi_pass_top_arc;
EDIT: changed my if statement to
vid_pData(7 downto 0) <= "00000000" when sw = '0';
and it got rid of the error but the implementation failed. The failure is:
[DRC MDRV-1] Multiple Driver Nets: Net
dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/vid_pData[0] has multiple
drivers: vid_pData_reg[0]/Q, and
dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/poData_reg[0]/Q.
You're not writing software, you're designing hardware. Your extra code drives signal vid_pData. So, does component dvi2rgb_0. So you have two drivers on that signal. A short circuit in other words.
Also, you do not say what value vid_pData should take if sw is not equal to '0'. Therefore, you will get latches in your hardware. (Google "inferring a latch".)
You need a new signal, eg:
signal vid_pData_new : std_logic_vector(23 downto 0);
then you need to assign a value for both sw equals '0' and '1', otherwise you will get a latch:
vid_pData_new(7 downto 0) <= vid_pData(23 downto 8) & "00000000" when sw = '0' else vid_pData;
The & operator is the concatenation operator. Finally, you need to drive component rgb2dvi_0 with your new signal:
rgb2dvi_inst : rgb2dvi_0
port map (
TMDS_Clk_p => tmds_tx_clk_p_o,
TMDS_Clk_n => tmds_tx_clk_n_o,
TMDS_Data_p => tmds_tx_data_p_o,
TMDS_Data_n => tmds_tx_data_n_o,
aRst => async_reset_i,
vid_pData => vid_pData_new, -- <-----------------
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => pixelclk
);
Can you see what has been done here? We have inserted a new piece of hardware that drives the new signal vid_pData_new and have specified its value for both possible values of sw. We must do this, otherwise we will get latches. We are designing hardware, not writing software.
I keep receiving an error while compiling my code below in quartus even though it does in the code below:
Error (12002): Port "qsys_dram_clk" does not exist in macrofunction "u0"
library ieee;
use ieee.std_logic_1164.all;
entity flappyroscoe is
port(
CLOCK_50 : IN STD_LOGIC := 'X';
CLOCK_27 : IN STD_LOGIC_VECTOR(0 downto 0);
AUD_XCK : OUT STD_LOGIC;
I2C_SDAT : INOUT STD_LOGIC := 'X';
I2C_SCLK : OUT STD_LOGIC;
AUD_ADCDAT : IN STD_LOGIC := 'X';
AUD_ADCLRCK : IN STD_LOGIC := 'X';
AUD_BCLK : IN STD_LOGIC := 'X';
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
DRAM_BA_1 : OUT STD_LOGIC;
DRAM_BA_0 : OUT STD_LOGIC;
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS =>
DRAM_UDQM : OUT STD_LOGIC;
DRAM_LDQM : OUT STD_LOGIC;
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC; VGA_VS : OUT STD_LOGIC;
VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DRAM_CLK : OUT STD_LOGIC
);
end entity;
architecture behavior of flappyroscoe is
component flappy_system is
port (
clk_clk: in std_logic:= 'X';
up_clocks_0_clk_in_secondary_clk: IN STD_LOGIC_VECTOR(0 downto 0);
up_clocks_0_audio_clk_clk: out std_logic;
audio_and_video_config_0_external_interface_SDAT : inout std_logic:= 'X';
audio_and_video_config_0_external_interface_SCLK : out std_logic;
audio_0_external_interface_ADCDAT : in std_logic:= 'X';
audio_0_external_interface_ADCLRCK : in std_logic:= 'X';
audio_0_external_interface_BCLK: in std_logic:= 'X';
qsys_dram_addr : out std_logic_vector(11 downto 0);
qsys_dram_ba : out std_logic_vector(1 downto 0);
qsys_dram_cas_n : out std_logic;
qsys_dram_cke: out std_logic;
qsys_dram_cs_n: out std_logic;
qsys_dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
qsys_dram_dqm : out std_logic_vector(1 downto 0);
qsys_dram_ras_n: out std_logic;
qsys_dram_we_n: out std_logic;
qsys_vga_HS: out std_logic;
qsys_vga_VS: out std_logic;
qsys_vga_R: out std_logic_vector(3 downto 0);
qsys_vga_G: out std_logic_vector(3 downto 0);
qsys_vga_B: out std_logic_vector(3 downto 0);
qsys_dram_clk: out std_logic
);
end component flappy_system;
signal dqm_sig,ba_sig: std_logic_vector(1 downto 0);
signal n: std_logic;
begin
DRAM_BA_1 <= ba_sig(1);
DRAM_BA_0 <= ba_sig(0);
DRAM_UDQM <= dqm_sig(1);
DRAM_LDQM <= dqm_sig(0);
u0 : component flappy_system
port map (
clk_clk => CLOCK_50,
up_clocks_0_clk_in_secondary_clk => CLOCK_27,
up_clocks_0_audio_clk_clk => AUD_XCK,
audio_and_video_config_0_external_interface_SDAT => I2C_SDAT,
audio_and_video_config_0_external_interface_SCLK => I2C_SCLK,
audio_0_external_interface_ADCDAT => AUD_ADCDAT,
audio_0_external_interface_ADCLRCK => AUD_ADCLRCK,
audio_0_external_interface_BCLK => AUD_BCLK,
qsys_dram_addr => dram_addr,
qsys_dram_ba => ba_sig,
qsys_dram_cas_n => dram_cas_n,
qsys_dram_cke => dram_cke,
qsys_dram_cs_n => dram_cs_n,
qsys_dram_dq => dram_dq,
qsys_dram_dqm => dqm_sig,
qsys_dram_ras_n => dram_ras_n,
qsys_dram_we_n => dram_we_n,
qsys_vga_HS => vga_HS,
qsys_vga_VS => vga_VS,
qsys_vga_R => vga_R,
qsys_vga_G => vga_G,
qsys_vga_B => vga_B,
qsys_dram_clk => DRAM_CLK
);
end architecture;
Error appears in translate phase that signal clkin2 has multiple drivers although it doesnt , main clock signal enters a DCM which generates 2 clock singles 1 acts as a clock for my vhdl module and other act as a clock for microblaze , the clkin2 is the clock of microblaze and its telling me it has multiple drivers ..
here is the code for my top vhdl :
-------------------------------------------------------------------------------
-- micro_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity micro_top is
port (
-- clkin: in std_logic;
fpga_0_RS232_Uart_1_RX_pin : in std_logic;
fpga_0_RS232_Uart_1_TX_pin : out std_logic;
fpga_0_DIP_Switches_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
fpga_0_Ethernet_MAC_MDINT_pin : in std_logic;
LED: out std_logic_vector(3 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_addr_pin : out std_logic_vector(12 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_ba_pin : out std_logic_vector(2 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_we_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_cke_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_clk_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_dq_pin : inout std_logic_vector(15 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_dqs_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udqs_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udm_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_ldm_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_odt_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin : out std_logic;
fpga_0_MCB_DDR3_rzq_pin : inout std_logic;
fpga_0_MCB_DDR3_zio_pin : inout std_logic;
fpga_0_clk_1_sys_clk_p_pin : in std_logic;
fpga_0_clk_1_sys_clk_n_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
-- xps_gpio_0_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_0_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_1_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_1_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_2_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_2_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_3_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_3_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
-- xps_gpio_4_GPIO_IO_O_pin : out std_logic_vector(0 to 3);
-- xps_gpio_5_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_5_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_6_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_6_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_7_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_7_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_8_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
-- xps_gpio_8_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
-- clock_generator_0_CLKOUT3_pin : out std_logic
);
end micro_top;
architecture STRUCTURE of micro_top is
component mycode is
port(
clk:in std_logic;
Input_1:in std_logic_vector((32)-1 downto 0);
Input_2:in std_logic_vector((32)-1 downto 0);
Input_3:in std_logic_vector((32)-1 downto 0);
Input_4:in std_logic_vector((32)-1 downto 0);
Input_5:in std_logic_vector((32)-1 downto 0);
Input_6:in std_logic_vector((32)-1 downto 0);
Input_7:in std_logic_vector((32)-1 downto 0);
Input_8:in std_logic_vector((32)-1 downto 0);
ready:in std_logic_vector(3 downto 0);
state:out std_logic_vector(3 downto 0);
Output_1:out std_logic_vector((32)-1 downto 0);
Output_2:out std_logic_vector((32)-1 downto 0);
Output_3:out std_logic_vector((32)-1 downto 0);
Output_4:out std_logic_vector((32)-1 downto 0);
Output_5:out std_logic_vector((32)-1 downto 0);
Output_6:out std_logic_vector((32)-1 downto 0);
Output_7:out std_logic_vector((32)-1 downto 0);
Output_8:out std_logic_vector((32)-1 downto 0)
);
end component;
component clk_wiz_v3_6 is
port (-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
component micro is
port (
fpga_0_RS232_Uart_1_RX_pin : in std_logic;
fpga_0_RS232_Uart_1_TX_pin : out std_logic;
fpga_0_DIP_Switches_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
fpga_0_Ethernet_MAC_PHY_tx_clk_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_clk_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_crs_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_dv_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_data_pin : in std_logic_vector(3 downto 0);
fpga_0_Ethernet_MAC_PHY_col_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rx_er_pin : in std_logic;
fpga_0_Ethernet_MAC_PHY_rst_n_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_tx_en_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_tx_data_pin : out std_logic_vector(3 downto 0);
fpga_0_Ethernet_MAC_PHY_MDC_pin : out std_logic;
fpga_0_Ethernet_MAC_PHY_MDIO_pin : inout std_logic;
fpga_0_Ethernet_MAC_MDINT_pin : in std_logic;
fpga_0_MCB_DDR3_mcbx_dram_addr_pin : out std_logic_vector(12 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_ba_pin : out std_logic_vector(2 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_we_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_cke_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_clk_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_dq_pin : inout std_logic_vector(15 downto 0);
fpga_0_MCB_DDR3_mcbx_dram_dqs_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udqs_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin : inout std_logic;
fpga_0_MCB_DDR3_mcbx_dram_udm_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_ldm_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_odt_pin : out std_logic;
fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin : out std_logic;
fpga_0_MCB_DDR3_rzq_pin : inout std_logic;
fpga_0_MCB_DDR3_zio_pin : inout std_logic;
fpga_0_clk_1_sys_clk_p_pin : in std_logic;
fpga_0_clk_1_sys_clk_n_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic;
xps_gpio_0_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_0_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_1_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_1_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_2_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_2_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_3_GPIO_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_3_GPIO2_IO_I_pin : in std_logic_vector(0 to 31);
xps_gpio_4_GPIO_IO_O_pin : out std_logic_vector(0 to 3);
xps_gpio_5_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_5_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_6_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_6_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_7_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_7_GPIO2_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_8_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
xps_gpio_8_GPIO2_IO_O_pin : out std_logic_vector(0 to 31)
-- clock_generator_0_CLKOUT3_pin : out std_logic
);
end component;
signal clkin :std_logic;
-- signal feedback :std_logic;
signal clkin2:std_logic;
signal xps_gpio_0_GPIO_IO_I_pin :std_logic_vector(0 to 31);
signal xps_gpio_0_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_1_GPIO_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_1_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_2_GPIO_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_2_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_3_GPIO_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_3_GPIO2_IO_I_pin : std_logic_vector(0 to 31);
signal xps_gpio_4_GPIO_IO_O_pin : std_logic_vector(0 to 3);
signal xps_gpio_5_GPIO_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_5_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_6_GPIO_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_6_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_7_GPIO_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_7_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_8_GPIO_IO_O_pin : std_logic_vector(0 to 31);
signal xps_gpio_8_GPIO2_IO_O_pin : std_logic_vector(0 to 31);
signal clock_generator_0_CLKOUT3_pin : std_logic;
attribute BUFFER_TYPE : STRING;
attribute BOX_TYPE : STRING;
attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_tx_clk_pin : signal is "IBUF";
attribute BUFFER_TYPE of fpga_0_Ethernet_MAC_PHY_rx_clk_pin : signal is "IBUF";
attribute BOX_TYPE of micro : component is "user_black_box";
begin
dcmer:clk_wiz_v3_6
port map (
CLK_IN1 =>fpga_0_clk_1_sys_clk_p_pin,
-- CLKFB_IN => open,
-- Clock out ports
CLK_OUT1=>clkin,
CLK_OUT2 =>clkin2
-- CLKFB_OUT => open
);
unit1 : mycode port map (
clk=>clkin,
Output_1=> xps_gpio_0_GPIO_IO_I_pin,
Output_2=> xps_gpio_0_GPIO2_IO_I_pin,
Output_3=> xps_gpio_1_GPIO_IO_I_pin,
Output_4=> xps_gpio_1_GPIO2_IO_I_pin,
Output_5=> xps_gpio_2_GPIO_IO_I_pin,
Output_6=> xps_gpio_2_GPIO2_IO_I_pin,
Output_7=> xps_gpio_3_GPIO_IO_I_pin,
Output_8=> xps_gpio_3_GPIO2_IO_I_pin,
ready=> xps_gpio_4_GPIO_IO_O_pin,
state=>LED,
Input_1=> xps_gpio_5_GPIO_IO_O_pin,
Input_2=> xps_gpio_5_GPIO2_IO_O_pin,
Input_3=> xps_gpio_6_GPIO_IO_O_pin,
Input_4=> xps_gpio_6_GPIO2_IO_O_pin,
Input_5=> xps_gpio_7_GPIO_IO_O_pin,
Input_6=> xps_gpio_7_GPIO2_IO_O_pin,
Input_7=> xps_gpio_8_GPIO_IO_O_pin,
Input_8=> xps_gpio_8_GPIO2_IO_O_pin
);
--LED<=xps_gpio_4_GPIO_IO_O_pin;
micro_i : micro
port map (
fpga_0_RS232_Uart_1_RX_pin => fpga_0_RS232_Uart_1_RX_pin,
fpga_0_RS232_Uart_1_TX_pin => fpga_0_RS232_Uart_1_TX_pin,
fpga_0_DIP_Switches_4Bit_GPIO_IO_pin => fpga_0_DIP_Switches_4Bit_GPIO_IO_pin,
fpga_0_Ethernet_MAC_PHY_tx_clk_pin => fpga_0_Ethernet_MAC_PHY_tx_clk_pin,
fpga_0_Ethernet_MAC_PHY_rx_clk_pin => fpga_0_Ethernet_MAC_PHY_rx_clk_pin,
fpga_0_Ethernet_MAC_PHY_crs_pin => fpga_0_Ethernet_MAC_PHY_crs_pin,
fpga_0_Ethernet_MAC_PHY_dv_pin => fpga_0_Ethernet_MAC_PHY_dv_pin,
fpga_0_Ethernet_MAC_PHY_rx_data_pin => fpga_0_Ethernet_MAC_PHY_rx_data_pin,
fpga_0_Ethernet_MAC_PHY_col_pin => fpga_0_Ethernet_MAC_PHY_col_pin,
fpga_0_Ethernet_MAC_PHY_rx_er_pin => fpga_0_Ethernet_MAC_PHY_rx_er_pin,
fpga_0_Ethernet_MAC_PHY_rst_n_pin => fpga_0_Ethernet_MAC_PHY_rst_n_pin,
fpga_0_Ethernet_MAC_PHY_tx_en_pin => fpga_0_Ethernet_MAC_PHY_tx_en_pin,
fpga_0_Ethernet_MAC_PHY_tx_data_pin => fpga_0_Ethernet_MAC_PHY_tx_data_pin,
fpga_0_Ethernet_MAC_PHY_MDC_pin => fpga_0_Ethernet_MAC_PHY_MDC_pin,
fpga_0_Ethernet_MAC_PHY_MDIO_pin => fpga_0_Ethernet_MAC_PHY_MDIO_pin,
fpga_0_Ethernet_MAC_MDINT_pin => fpga_0_Ethernet_MAC_MDINT_pin,
fpga_0_MCB_DDR3_mcbx_dram_addr_pin => fpga_0_MCB_DDR3_mcbx_dram_addr_pin,
fpga_0_MCB_DDR3_mcbx_dram_ba_pin => fpga_0_MCB_DDR3_mcbx_dram_ba_pin,
fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin => fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin => fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_we_n_pin => fpga_0_MCB_DDR3_mcbx_dram_we_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_cke_pin => fpga_0_MCB_DDR3_mcbx_dram_cke_pin,
fpga_0_MCB_DDR3_mcbx_dram_clk_pin => fpga_0_MCB_DDR3_mcbx_dram_clk_pin,
fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin => fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_dq_pin => fpga_0_MCB_DDR3_mcbx_dram_dq_pin,
fpga_0_MCB_DDR3_mcbx_dram_dqs_pin => fpga_0_MCB_DDR3_mcbx_dram_dqs_pin,
fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin => fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_udqs_pin => fpga_0_MCB_DDR3_mcbx_dram_udqs_pin,
fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin => fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin,
fpga_0_MCB_DDR3_mcbx_dram_udm_pin => fpga_0_MCB_DDR3_mcbx_dram_udm_pin,
fpga_0_MCB_DDR3_mcbx_dram_ldm_pin => fpga_0_MCB_DDR3_mcbx_dram_ldm_pin,
fpga_0_MCB_DDR3_mcbx_dram_odt_pin => fpga_0_MCB_DDR3_mcbx_dram_odt_pin,
fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin => fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin,
fpga_0_MCB_DDR3_rzq_pin => fpga_0_MCB_DDR3_rzq_pin,
fpga_0_MCB_DDR3_zio_pin => fpga_0_MCB_DDR3_zio_pin,
fpga_0_clk_1_sys_clk_p_pin => clkin2,
fpga_0_clk_1_sys_clk_n_pin => fpga_0_clk_1_sys_clk_n_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
xps_gpio_0_GPIO_IO_I_pin => xps_gpio_0_GPIO_IO_I_pin,
xps_gpio_0_GPIO2_IO_I_pin => xps_gpio_0_GPIO2_IO_I_pin,
xps_gpio_1_GPIO_IO_I_pin => xps_gpio_1_GPIO_IO_I_pin,
xps_gpio_1_GPIO2_IO_I_pin => xps_gpio_1_GPIO2_IO_I_pin,
xps_gpio_2_GPIO_IO_I_pin => xps_gpio_2_GPIO_IO_I_pin,
xps_gpio_2_GPIO2_IO_I_pin => xps_gpio_2_GPIO2_IO_I_pin,
xps_gpio_3_GPIO_IO_I_pin => xps_gpio_3_GPIO_IO_I_pin,
xps_gpio_3_GPIO2_IO_I_pin => xps_gpio_3_GPIO2_IO_I_pin,
xps_gpio_4_GPIO_IO_O_pin => xps_gpio_4_GPIO_IO_O_pin,
xps_gpio_5_GPIO_IO_O_pin => xps_gpio_5_GPIO_IO_O_pin,
xps_gpio_5_GPIO2_IO_O_pin => xps_gpio_5_GPIO2_IO_O_pin,
xps_gpio_6_GPIO_IO_O_pin => xps_gpio_6_GPIO_IO_O_pin,
xps_gpio_6_GPIO2_IO_O_pin => xps_gpio_6_GPIO2_IO_O_pin,
xps_gpio_7_GPIO_IO_O_pin => xps_gpio_7_GPIO_IO_O_pin,
xps_gpio_7_GPIO2_IO_O_pin => xps_gpio_7_GPIO2_IO_O_pin,
xps_gpio_8_GPIO_IO_O_pin => xps_gpio_8_GPIO_IO_O_pin,
xps_gpio_8_GPIO2_IO_O_pin => xps_gpio_8_GPIO2_IO_O_pin
-- clock_generator_0_CLKOUT3_pin => clock_generator_0_CLKOUT3_pin
);
end architecture STRUCTURE;
and here is the code of DCM component :
-- file: clk_wiz_v3_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
-- CLK_OUT2___100.000______0.000_______N/A________0.000________N/A
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clk_wiz_v3_6;
architecture xilinx of clk_wiz_v3_6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=5.0,clkin2_period=5.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfx : std_logic;
signal clkfx180_unused : std_logic;
signal clkfxdv : std_logic;
signal clkfbout : std_logic;
-- Dynamic programming unused signals
signal progdone_unused : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(2 downto 1);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_clkgen_inst: DCM_CLKGEN
generic map
(CLKFXDV_DIVIDE => 2,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 2,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 5.0,
CLKFX_MD_MAX => 0.000)
port map
-- Input clock
(CLKIN => clkin1,
-- Output clocks
CLKFX => clkfx,
CLKFX180 => clkfx180_unused,
CLKFXDV => clkfxdv,
-- Ports for dynamic phase shift
PROGCLK => '0',
PROGEN => '0',
PROGDATA => '0',
PROGDONE => progdone_unused,
-- Other control and status signals
FREEZEDCM => '0',
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0');
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkfx;
CLK_OUT2 <= clkfxdv;
end xilinx;
Thanks in advance
If fpga_0_clk_1_sys_clk_p_pin and fpga_0_clk_1_sys_clk_n_pin are signals of a differential clock, you should instantiate a IBUFGDS or something like that (check the clocking resources manual of your FPGA family for details)
Thanks to the idea of baldyhdl the problem was entering to the micro blaze a clock signal from PLL and another one directly from N pin of the differential clock , correct solution was to change micro blaze clock from differential clock to single ended and use differential clock to produce 2 clocks , one for microblaze while other for the rest of the design,
Thanks for the help
I'm trying to implement a VHDL project but I'm having problems connecting the different components correctly. I just want to make sure that I did this correctly. The code below is just the wrapper (which, to this point, is where the problem lies). Please let me know if I'm connecting the input and outputs to each component correctly.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SodaWrapper is
Port ( PB1 : in STD_LOGIC;
PB2 : in STD_LOGIC;
PB3 : in STD_LOGIC;
PB4 : in STD_LOGIC;
clk_50m : in STD_LOGIC;
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC;
LED3 : out STD_LOGIC;
LED4 : out STD_LOGIC;
seven_seg1 : out STD_LOGIC_VECTOR(7 downto 0);
seven_seg2 : out STD_LOGIC_VECTOR(7 downto 0));
end SodaWrapper;
architecture Behavioral of SodaWrapper is
--Define debounce components
component debounce
port (clk : in STD_LOGIC;
reset : in STD_LOGIC;
sw : in STD_LOGIC;
db_level: out STD_LOGIC;
db_tick: out STD_LOGIC);
end component;
for all : debounce use entity work.debounce(debounce);
--define clock
component Clock_Divider
port(
clk : in STD_LOGIC;
clockbus : out STD_LOGIC_VECTOR(26 downto 0)
);
end component;
for all : Clock_Divider use entity work.Clock_Divider(Clock_Divider);
COMPONENT SodaMachine_Moore
PORT(
CLK : IN std_logic;
Reset : IN std_logic;
Nickel : IN std_logic;
Dime : IN std_logic;
Quarter : IN std_logic;
Dispense : OUT std_logic;
ReturnNickel : OUT std_logic;
ReturnDime : OUT std_logic;
ReturnTwoDimes : OUT std_logic;
change1 : OUT std_logic_vector(3 downto 0);
change2 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define sseg_converter components
component hex_to_sseg
port( dp : in STD_LOGIC;
hex : in STD_LOGIC_VECTOR(3 downto 0);
sseg : out STD_LOGIC_VECTOR(7 downto 0));
end component;
--create wire for FSM to sseg converter
signal hexconvertones : STD_LOGIC_VECTOR(3 downto 0);
signal hexconverttens : STD_LOGIC_VECTOR(3 downto 0);
--create wires for output of debouncers
signal db_tick_n : STD_LOGIC;
signal db_tick_d : STD_LOGIC;
signal db_tick_q : STD_LOGIC;
signal IQ_n : STD_LOGIC;
signal IQ_d : STD_LOGIC;
signal IQ_q : STD_LOGIC;
--wire up clock
signal clockingbus : STD_LOGIC_VECTOR(26 downto 0);
begin
-- Setup the clock
clock1 : Clock_divider port map (
clk => clk_50m,
clockbus => clockingbus
);
-- Link debounce to FSM
debounce_n : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB1,
db_tick => db_tick_n
);
debounce_d : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB2,
db_tick => db_tick_d
);
debounce_q : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB3,
db_tick => db_tick_q
);
--invert values of db_tick since logic value of button pressed is 0 and vice versa
IQ_n <= not(db_tick_n);
IQ_d <= not(db_tick_d);
IQ_q <= not(db_tick_q);
-- Link components to main FSM
main : SodaMachine_Moore PORT MAP (
CLK => clockingbus(0),
Reset => PB4,
Nickel => IQ_n,
Dime => IQ_d,
Quarter => IQ_q,
Dispense => LED1,
ReturnNickel => LED2,
ReturnDime => LED3,
ReturnTwoDimes => LED4,
change1 => hexconvertones,
change2 => hexconverttens
);
--Link seven segment display to FSM
change_ones : hex_to_sseg port map('0', hexconvertones, seven_seg1);
change_tens : hex_to_sseg port map('0', hexconverttens, seven_seg2);
end Behavioral;