vhdl code wrapper - vhdl

Question

I'm trying to implement a VHDL project but I'm having problems connecting the different components correctly. I just want to make sure that I did this correctly. The code below is just the wrapper (which, to this point, is where the problem lies). Please let me know if I'm connecting the input and outputs to each component correctly.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SodaWrapper is
Port ( PB1 : in STD_LOGIC;
PB2 : in STD_LOGIC;
PB3 : in STD_LOGIC;
PB4 : in STD_LOGIC;
clk_50m : in STD_LOGIC;
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC;
LED3 : out STD_LOGIC;
LED4 : out STD_LOGIC;
seven_seg1 : out STD_LOGIC_VECTOR(7 downto 0);
seven_seg2 : out STD_LOGIC_VECTOR(7 downto 0));
end SodaWrapper;
architecture Behavioral of SodaWrapper is
--Define debounce components
component debounce
port (clk : in STD_LOGIC;
reset : in STD_LOGIC;
sw : in STD_LOGIC;
db_level: out STD_LOGIC;
db_tick: out STD_LOGIC);
end component;
for all : debounce use entity work.debounce(debounce);
--define clock
component Clock_Divider
port(
clk : in STD_LOGIC;
clockbus : out STD_LOGIC_VECTOR(26 downto 0)
);
end component;
for all : Clock_Divider use entity work.Clock_Divider(Clock_Divider);
COMPONENT SodaMachine_Moore
PORT(
CLK : IN std_logic;
Reset : IN std_logic;
Nickel : IN std_logic;
Dime : IN std_logic;
Quarter : IN std_logic;
Dispense : OUT std_logic;
ReturnNickel : OUT std_logic;
ReturnDime : OUT std_logic;
ReturnTwoDimes : OUT std_logic;
change1 : OUT std_logic_vector(3 downto 0);
change2 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define sseg_converter components
component hex_to_sseg
port( dp : in STD_LOGIC;
hex : in STD_LOGIC_VECTOR(3 downto 0);
sseg : out STD_LOGIC_VECTOR(7 downto 0));
end component;
--create wire for FSM to sseg converter
signal hexconvertones : STD_LOGIC_VECTOR(3 downto 0);
signal hexconverttens : STD_LOGIC_VECTOR(3 downto 0);
--create wires for output of debouncers
signal db_tick_n : STD_LOGIC;
signal db_tick_d : STD_LOGIC;
signal db_tick_q : STD_LOGIC;
signal IQ_n : STD_LOGIC;
signal IQ_d : STD_LOGIC;
signal IQ_q : STD_LOGIC;
--wire up clock
signal clockingbus : STD_LOGIC_VECTOR(26 downto 0);
begin
-- Setup the clock
clock1 : Clock_divider port map (
clk => clk_50m,
clockbus => clockingbus
);
-- Link debounce to FSM
debounce_n : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB1,
db_tick => db_tick_n
);
debounce_d : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB2,
db_tick => db_tick_d
);
debounce_q : debounce port map (
clk => clockingbus(0),
reset => PB4,
sw => PB3,
db_tick => db_tick_q
);
--invert values of db_tick since logic value of button pressed is 0 and vice versa
IQ_n <= not(db_tick_n);
IQ_d <= not(db_tick_d);
IQ_q <= not(db_tick_q);
-- Link components to main FSM
main : SodaMachine_Moore PORT MAP (
CLK => clockingbus(0),
Reset => PB4,
Nickel => IQ_n,
Dime => IQ_d,
Quarter => IQ_q,
Dispense => LED1,
ReturnNickel => LED2,
ReturnDime => LED3,
ReturnTwoDimes => LED4,
change1 => hexconvertones,
change2 => hexconverttens
);
--Link seven segment display to FSM
change_ones : hex_to_sseg port map('0', hexconvertones, seven_seg1);
change_tens : hex_to_sseg port map('0', hexconverttens, seven_seg2);
end Behavioral;