Error Compiling in quartus - vhdl

Question

I keep receiving an error while compiling my code below in quartus even though it does in the code below:
Error (12002): Port "qsys_dram_clk" does not exist in macrofunction "u0"
library ieee;
use ieee.std_logic_1164.all;
entity flappyroscoe is
port(
CLOCK_50 : IN STD_LOGIC := 'X';
CLOCK_27 : IN STD_LOGIC_VECTOR(0 downto 0);
AUD_XCK : OUT STD_LOGIC;
I2C_SDAT : INOUT STD_LOGIC := 'X';
I2C_SCLK : OUT STD_LOGIC;
AUD_ADCDAT : IN STD_LOGIC := 'X';
AUD_ADCLRCK : IN STD_LOGIC := 'X';
AUD_BCLK : IN STD_LOGIC := 'X';
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
DRAM_BA_1 : OUT STD_LOGIC;
DRAM_BA_0 : OUT STD_LOGIC;
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS =>
DRAM_UDQM : OUT STD_LOGIC;
DRAM_LDQM : OUT STD_LOGIC;
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
VGA_HS : OUT STD_LOGIC; VGA_VS : OUT STD_LOGIC;
VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DRAM_CLK : OUT STD_LOGIC
);
end entity;
architecture behavior of flappyroscoe is
component flappy_system is
port (
clk_clk: in std_logic:= 'X';
up_clocks_0_clk_in_secondary_clk: IN STD_LOGIC_VECTOR(0 downto 0);
up_clocks_0_audio_clk_clk: out std_logic;
audio_and_video_config_0_external_interface_SDAT : inout std_logic:= 'X';
audio_and_video_config_0_external_interface_SCLK : out std_logic;
audio_0_external_interface_ADCDAT : in std_logic:= 'X';
audio_0_external_interface_ADCLRCK : in std_logic:= 'X';
audio_0_external_interface_BCLK: in std_logic:= 'X';
qsys_dram_addr : out std_logic_vector(11 downto 0);
qsys_dram_ba : out std_logic_vector(1 downto 0);
qsys_dram_cas_n : out std_logic;
qsys_dram_cke: out std_logic;
qsys_dram_cs_n: out std_logic;
qsys_dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
qsys_dram_dqm : out std_logic_vector(1 downto 0);
qsys_dram_ras_n: out std_logic;
qsys_dram_we_n: out std_logic;
qsys_vga_HS: out std_logic;
qsys_vga_VS: out std_logic;
qsys_vga_R: out std_logic_vector(3 downto 0);
qsys_vga_G: out std_logic_vector(3 downto 0);
qsys_vga_B: out std_logic_vector(3 downto 0);
qsys_dram_clk: out std_logic
);
end component flappy_system;
signal dqm_sig,ba_sig: std_logic_vector(1 downto 0);
signal n: std_logic;
begin
DRAM_BA_1 <= ba_sig(1);
DRAM_BA_0 <= ba_sig(0);
DRAM_UDQM <= dqm_sig(1);
DRAM_LDQM <= dqm_sig(0);
u0 : component flappy_system
port map (
clk_clk => CLOCK_50,
up_clocks_0_clk_in_secondary_clk => CLOCK_27,
up_clocks_0_audio_clk_clk => AUD_XCK,
audio_and_video_config_0_external_interface_SDAT => I2C_SDAT,
audio_and_video_config_0_external_interface_SCLK => I2C_SCLK,
audio_0_external_interface_ADCDAT => AUD_ADCDAT,
audio_0_external_interface_ADCLRCK => AUD_ADCLRCK,
audio_0_external_interface_BCLK => AUD_BCLK,
qsys_dram_addr => dram_addr,
qsys_dram_ba => ba_sig,
qsys_dram_cas_n => dram_cas_n,
qsys_dram_cke => dram_cke,
qsys_dram_cs_n => dram_cs_n,
qsys_dram_dq => dram_dq,
qsys_dram_dqm => dqm_sig,
qsys_dram_ras_n => dram_ras_n,
qsys_dram_we_n => dram_we_n,
qsys_vga_HS => vga_HS,
qsys_vga_VS => vga_VS,
qsys_vga_R => vga_R,
qsys_vga_G => vga_G,
qsys_vga_B => vga_B,
qsys_dram_clk => DRAM_CLK
);
end architecture;