I have a pretty elementary question which is somewhat confusing me. It will be great to get some refresher on this.
Every computer has a word size. The word size is the maximum size of the virtual address space. So if we have lets say a 32 bit word size, we have a virtual address space that ranges to a max of 2^32 values. In references it says 2^32 bytes? Why is the range in bytes.
Also, What I am failing to understand is how 2^32 possible values be a possible address range of 4GB? So, my confusion stems from the confusion of turning the 32 bit word size into 4 byte word size, and then how 4 bytes, multiplied 2^32 times result in 4GB.
One way I tried to rationalize it is as follows:
2^32 bits = 2^2(bytes) x 2^10(kilobytes) x 2^10(megabytes) x 2^10(gigabytes)
So successive division of 2^32 by 2^10 results in 2^2 GB or 4 GB.
Can somebody point out how the 32-bit word size go to a 4GB page range?
Thanks
The argument in my head goes like this: We have 32 bits available to us, each bit can be at most 1. So the largest number we can accommodate is when all 32 bits (the 0 bit to the 31 bit that is) are filled with 1s. So the trick is to find the largest number in decimal form, by converting from binary to decimal we get:
1111111111111111111111111111111 (binary) = 4294967295 (decimal)
But what is 4294967295? It's actually one less than 2^32. Now there's another important thing to keep in mind:
4GB = 4294967296 bytes
But why is it 1 greater than our result? Because our first byte is byte 0 while the last is byte 4294967295 for a total of 4294967296 bytes.
So now we're in a position where the smallest number that can exist in a 32-bit register is 0 and the largest number that can exist in a 32-bit register is 4294967295.
0 (binary) - 1111111111111111111111111111111 (binary)
0 (decimal) - 4294967295 (decimal)
0 (hex) - 0xFFFFFFFF (hex)
So there is 4GB of addressable space because anything above 4GB will have an address that is too big of a number to fit inside a 32-bit number and thus inside a 32-bit register.
I did all this stuff inside excel and seeing it helped me a lot.
Related
Encountered this problem and the solution said
"32 bit address bits, 64 byte line means we have 6 bits for the word address in the line that aren't in the tag, 32,768 bytes in the cache at 64 byte lines is 512 total lines, which means we have 12 bits of address for the cache index, write back means we need a dirty bit, and we always need a valid bit. So each line has 64*8=512 data bits, 32-6- 12=14 tag bits, and 2 flag bits: data/total bits = 512/(512+14+2)=512/528."
When I tried to solve the problem I got 32kB/64byte=512 lines in total, i.e. 2^9=512. In addition, a 64 byte cache line size, 1 word=4 bytes, is 64/4=16 words per line i.e. 2^4.
To my understanding the total amount of bits in a cache is given by total amount of entries/lines in the caches*(tag address + data)-> 2^9*((32-9-4+2)+16*32). Thus, the amount of data bits per cache line is 512 (16 words *32 bits per word), and the tag is 32-9-4+2=21 (the 9 is the cache index for direct mapped cache, the 4 is to address each word and the 2 is the valid bit and dirty bit)
Effectively, the answer should be 512/533 and not 512/528.
Correct?
512 lines = 9 bits not 12 as they claim, so you are right on this point.
However, they are right that 64 byte lines gives 6 bits for the block offset — though it is a byte offset, not word as they say.
So, 32-6-9=17 tag bits, then plus the 2 for dirty & valid.
FYI, there's nothing in the above problem that indicates a conversion from bytes to words. While it is true that there will be 16 x 32-bit words per line (i.e. 64 bytes per line) it is irrelevant: we should presume that the 32-bit address is a byte address unless otherwise stated. (It would be unusual to state cache size in bytes for a word (not byte) addressable machine; it would also be unusual for a 32-bit machine to be word addressable — some teaching architectures like LC-3 are word addressable, however, they are 16-bits; other word addressable machines have odd sizes like 12 or 18 or 36 bit words — though those pre-date caches!)
virtual adress size: 32 bits
page size = 4K =2^12 bytes
what is the number of pages?
i know the answer is (2^32)/(2^12) = 2^20 but why?
i think it should be (2^32)/(2^15) because of the byte bit conversion (2^12)*(8)=2^15
Every byte in memory has a numeric address starting from 0. The CPU has one or more registers which hold the address of that one byte which is being worked upon. A register is a physical device and has limits to how large a number it can store.
virtual address size: 32 bits
This means the address register can store one address (number) which could be anything between 0 and 2^32 -1.
As the largest address that the address register can store is 2^32 -1 there is no point in having more memory bytes. Because the CPU will never be able to work with them. So in general we assume the total memory to be 2^32 bytes.
page size = 4K =2^12 bytes
The total memory of millions of bytes is actually organized in chunks called pages. Here total memory of 2^32 bytes is chunked into pages of 2^12 bytes.
what is the number of pages?
the answer is (2^32)/(2^12) = 2^20. Good job!
but why? i think it should be (2^32)/(2^15) because of the byte bit conversion (2^12)*(8)=2^15
Here 2^32 is the total number of bytes in memory. 2^12 is total number of bytes in a page. Both numerator and denominator should be in same units - bytes. So you need not convert the denominator to bits.
Note:
I have used over simplification of terms like memory, address, register etc. Many of the statements made above are not valid for a real laptop - but useful for initial learning.
Preface: There are many different design patterns that are important to cache's overall performance. Below are listed parameters for
different direct-mapped cache designs.
Cache data size: 32 kib
Cache block Size: 2 words
Cache access time: 1-cycle
Question: Calculate the number of bits required for the cache listed above, assuming a 32-bit address. Given that total size, find the
total size of the closest direct-mapped cache with 16-word blocks of
equal size or greater. Explain why the second cache, despite its
larger data size, might provide slower performance that the first
cache.
Here's the formula:
Number of bits in a cache 2^n X (block size + tag size + valid field size)
Here's what I got: 65536(1+14X(32X2)..
is this correct?
using: (2^index bits) * (valid bits + tag bits + (data bits * 2^offset bits))
for the first one i get:
total bits = 2^15 (1+14+(32*2^1)) = 2588672 bits
for the cache with 16 word blocks i get:
total bits = 2^13(1 +13+(32*2^4)) = 4308992
the next smallest cache with 16 word blocks and a 32 bit address works out to be 2158592 bits, smaller than the first cache.
I'm stuck on the same problem too but I have the answer to the first part.
To calculate the total number of bits required
You need to convert the KB to words and get the index bits.
Use the answer from part 1 to get your tag bits.
Plug them into this formula.
(2^(index bits)) * ((tag bits)+(valid bits)+(data size))
Hint: data size is 64 bits in this case and valid bit is 1. So just find the index and tag bits.
And I don't think your answer is right. I didn't check but I can see you are multiplying 1+14 and (32x2) instead of adding them.
I think the formula you were using is correct. According to my textbook "Computer Organization and Design The Hardware, 5th edition", the total number of bits in a direct-mapped cache is:
2^indext bits * (block size + tag size + valid field size).
block size was given by the question: 2 words = 32 bits
tag size: 32 - offset in bits - index in bits
valid field size is usually 1 valid bit
Let’s say we have a 32-bit address, so each bit can be either 1 or 0.
So the total number of combinations is equal to 2^32.
So we can represent 2^32 addresses (without unit).
But why do people say a 32-bit address can represent 2^32 byte addresses (why “byte” addresses)?
I already read Why does a 32-bit OS support 4 GB of RAM?
Won’t it become 2^32 * 8 bits addresses? Why can people simply add “byte” at the end?
Because memory is byte-addressable rather than bit-addressable.
The address 0x100 refers to a single byte and the address 0x101 refers the following byte.
Each address points to a byte. In memory, it is not the single bits that are addressed but instead bytes.
So, 32bits will give you an addressable space of 2^32 items, each item being a full byte. Yes, it could have been made so that each address points to a specific bit, but no, they made each address point to a byte.
I have a very simple (n00b) question.
A 20-bit external address bus gave a 1 MB physical address space (2^20
= 1,048,576).(Wikipedia)
Why 1 MByte?
2^20 = 1,048,576 bit = 1Mbit = 128KByte not 1MB
I misunderstood something.
When you have 20 bits you can address up to 2^20. This is your range, not the number of bits.
I.e. if you have 8 bits your range is up to 255 (unsigned) not 2^8 bits.
So with 20 bits you can address up to 2^20 bytes i.e. 1MB
I.e. with 20 bits you can represent addresses from 0 up to 2^20 = 1,048,576. I.e. you can reference up to 1MB of memory.
1 << 20 addresses, that is 1,048,576 bytes addressable. Hence, 1 MB physical address space.
Because the smallest addressable unit of memory (in general - some architectures have small bit-addressable pieces of memory) is the byte, not the bit. That is, each address refers to a byte, rather than to a bit.
Why, you ask? Direct access to individual bits is almost never needed - and if you need it, you can still load the surrounding byte and get the bit with bit masks and shifts. Increasing the bits per address allows you to address more memory with the same address range.
Note that a byte doesn't have to be 8 bit, strictly speaking, though it's ubiquitous by now. But regardless of the byte size, you're grouping bits together to be able to handle larger quantities of them.