I created a Makefile.in where I read the content out of a file and pass it to CFLAGS. Calling ./configure ... the Makefile will be generated an all works well.
Makefile.in:
...
MY_REVISION_FILE=my-revision.txt
MY_REVISION=$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))
AM_CFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=$(MY_REVISION)
...
The problem arises once I moved the Makefile.in code into Makefile.am to allow the auto generation of Makefile.in. There calling autoreconf -i --force stops with the following error:
server/Makefile.am:9: cat $(top_srcdir: non-POSIX variable name
server/Makefile.am:9: (probably a GNU make extension)
autoreconf: automake failed with exit status: 1
This problem hunts me now since quite some time. I searched everywhere but did not find anything that could help me finding a solution for that. In short, the only thing I need is a way to get an uninterpreted text such as "$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))" copied from Makefile.am to Makefile.in
Any idea?
Thanks,
Oliver
As it says, the problem is you're using a GNUism in your Makefile.am, when it's only meant to contain portable Makefile code.
Either rewrite your code so it's portable (you should use AM_CPPFLAGS because you're passing flags to the preprocessor, not the compiler):
AM_CPPFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=`cat $(top_srcdir)/$(MY_REVISION_FILE)`
If you don't want to invoke cat on every compile, you could find the value in configure.ac and either AC_SUBST it into Makefile or AC_DEFINE it so it goes into config.h.
Or if you want to be non-portable (ಠ_ಠ), you can take -Werror out of your AM_INIT_AUTOMAKE or AUTOMAKE_OPTIONS, or add -Wno-portability.
After long testing back and forth I decided to use AC_SUBST.
My solution might not be the cleanest but it works for me.
In configure.ac I added the following line
AC_SUBST([DOLLAR_SIGN],[$])
In the Makefile.am I changed my previous line into
MY_REVISION=#DOLLAR_SIGN#(shell cat $(SRC_DIR)/$(MY_REVISION_FILE))
And it works.
Again, thanks for your help.
Related
I'm working with autotools for the first time, for a tool that's written in perl (SQLTeX), so only installation is required, no compilation.
The toplevel contains a simple Makefile.am:
AUTOMAKE_OPTIONS = foreign
SUBDIRS = src man doc
EXTRA_DIST = README.md
.PHONY: all-am
all-am:
#echo "Done!"
If I create Makefile.am files in the sub-directories too, nothing seems to happen there so I just stick to Makefile. A snippet from src/Makefile (EDIT: this file is now renamed to Makefile.am):
SQLTeX: SQLTeX.pl
cat $^ | sed -e 's#{PERLDIR}#$(PL)#;s#{SYSCONFDIR}#$(sysconfdir)#' > $#
#chmod +x $#
The symbol PL is set as expect (defined in the same makefile), but sysconfdir is empty, although it is defined in the top-level Makefile generated by ./configure.
What am I doing wrong?
Thanks in advance!
What am I doing wrong?
Although the Autotools support, with some caveats, recursing into directories where you provide pre-built makefiles, you cannot expect those pre-built makefiles to be able to rely on autotools-provided variables such as the standard directory variables bindir and sysconfdir. Thus, although it is allowed to rely on hand-written makefiles in subdirectories, this is probably a false trail for you.
I recommend going back to this:
If I create Makefile.am files in the sub-directories too, nothing seems to happen there
and working out what's wrong. The Autotools definitely support generating recursive build systems, and one Makefile.am per directory is part of the usual approach to that. If it didn't work for you then my first guess would be that you forgot to list the extra makefiles in your AC_CONFIG_FILES list.
As an alternative, just because you have multiple directories does not mean that you need to use recursive make. It is quite possible to build such a project with the support of a single makefile, and the Autotools can help with such a makefile.
I am trying to include MPI compiler to my makefile. The makefile is already prepared such that I only need to include the address of the MPI compiler in a a separate env file. However doing so does not work. I can get the cpp file to run manually by typing:
mpicxx Demo_00.cpp -o aprogram
./aprogram
I test where the mpi compiler is located using:
which mpicxx
/usr/bin/mpicxx
In the env file the corresponding line is:
MPICXX=/usr/bin/mpicxx
However, when I try to 'make' he cpp file I get the following error:
make Demo_00
g++ Demo_00.cpp -o Demo_00
Demo_00.cpp:2:17: fatal error: mpi.h: No such file or directory
compilation terminated.
make: *** [Demo_00] Error 1
The cpp file is in the same folder as the env file and the makefile.
I am not quite sure how to identify the error.
Thank you for your help,
Tartaglia
If you want to change the name of the C++ compiler, you have to change the variable CXX. That's the default variable make uses when it wants to compile C++ code.
This line in your log file:
g++ Demo_00.cpp -o Demo_00
says that you are using g++ compiler instead of mpixx.
Usually in makefiles compiler definition is at the beginnig of the file and looks like this:
CC=g++
just change it to mpixx
CC=mpixx
Thank you all for your responses, I took a closer look into the makefile I thought I was using and it turns out, as you have already suggested, I was not using it at all. The makefile was only able to execute one specific cpp file with one specific name. So whenever I typed in make *.cpp I was using the standard make as you already pointed out.
Thanks again for your help.
I'm new to using makefiles and trying to produce a basic makefile as part of an exercise for university. I have two source code files, chello.c and writeexit.s, which have to be compiled/assembled and then linked to produce chello.
This is the code I have so far for the makefile:
chello: chello.o writeexit.o
ld -N chello.o writeexit.o -o chello
chello.o: chello.c
gcc -c chello.c -o chello.o
writeexit.o: writeexit.s
as writeexit.s -o writeexit.o
The whitespace before ld, gcc and as are all tabs, so I think the whitespacing is fine. When I call 'make makefile', it returns 'make: Nothing to be done for `makefile'.' However, if I change the dependencies of chello, like chello.c, the same message is returned and chello's behaviour is not modified.
From man make:
make executes commands in the makefile to update one or more target
names, where name is typically a program. If no -f option is present,
make will look for the makefiles GNUmakefile, makefile, and Makefile,
in that order.
make makefile will actually execute your "makefile" (because it is listed among the default names in the man page) file, trying to build the "makefile" target (because of the argument you are passing), which already exists
What you need is to build the "chello" binary, so you have to type:
make chello
Or alternatively:
make -f makefile chello
Alternative account here, it seems to work fine if I just call "make" instead of "make makefile". This question can be ignored.
All,
I'm trying to pass variables to make from the command line. My command is below
make ARCH=arm CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-g++
The error I received is
g++: error: arm: No such file or directory
But the file 'arm-openwrt-linux-g++' does exist.
I think the problem is I need to pass varibale to sub-make files. Can some help with an example of how to pass varialbes to sub-makefile from the command-line. I have tried using the -e and export options for make, but can't seen to get anything to work.
Thanks
Content of makefile:
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
#echo "==== Building json ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
#echo "==== Building openjaus ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f openjaus.make
So, your problem is not related to sending variables over the command line.
Your problem is that in one of the makefiles in your sub-directories, which you haven't shown us, you're using the variable $(ARCH) in an incorrect way such that the expansion of the command line is not a legal g++ command line.
Based on the error message, most likely you're adding a space somewhere where it shouldn't be, so instead of something like -fmarch=arm you're getting -fmarch= arm. Obviously this is just an example because you didn't provide nearly enough information.
One other note: we can't know how your makefiles work but typically makefiles that support a variable like CROSS_COMPILE expect it to be set to just the prefix of the cross-compilation command; in your case it would be CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-. But, your makefiles might be different.
When asking questions, it's best to if you don't immediately jump to a guess about what the answer is. First describe the problem, and that includes showing the error line as well as a few lines before it. For example in this case you're getting an error from g++ so the command line that make printed out showing you how it invoked g++ would have helped greatly.
Once you've given the underlying detail, then if you think you have an idea about what the problem is go ahead and suggest it, and/or ask about it.
If you provide the rule that invokes g++ and/or the output from make showing the g++ command line, then we can help more.
Cheers!
Here's what I think needs to happen:
You need to make sure that your sub-makefiles actually respect the $(ARCH) and $(CROSS_COMPILE) variables. Are they also generated by Premake? If so, is that how it handles cross-compilation? Check the docs.
In my test (below), I found that variables set on the command line are propagated to sub-makes, which makes me think that your sub-makefiles aren't respecting $(ARCH):
Makefile:
a:
$(MAKE) -C z
z/Makefile:
a:
#echo "MAKE=$(MAKE)"
#echo "ARCH=$(ARCH)"
Running make with no arguments:
$ make
make -C z
make[1]: Entering directory `/home/foo/test/z'
MAKE=make
ARCH=
make[1]: Leaving directory `/home/foo/test/z'
Running make ARCH=bar:
$ make ARCH=bar
make -C z
make[1]: Entering directory `/home/foo/z/z'
MAKE=make
ARCH=bar
make[1]: Leaving directory `/home/foo/z/z'
I am looking at C makefile, and I have a question.
I know that 'make a' will make the target a, which is supposed to be defined in the makefile.
I want to know whether the target name itself can be supplied as an argument to make.
i.e. this is what I want to do:
$(target_name) is the name supplied to command 'make'. For example, 'make foo'.
and in the makefile,
$(target_name) = dependencies
command
I am not sure whether this is possible... could not find anything in the make manual too.
If anyone can help me with this, it'll be awesome.
Thanks,
Everything you are asking about is what make does by default - there is no need to write any special code in the makefile to do this. You seem rather confused about make (it is not particularly C related, for example). The best guide to it is the GNU Make Manual, which is not only a manual but a pretty good tutorial.
I'm kind of new to Makefiles but it seems you don't pass values in Makefile like that. If the following is your Makefile
# Makefile
TARGET?=something
$(TARGET):
echo $(TARGET)
You can pass parameters in by calling make like this in the terminal
$ TARGET='ABCDEF' make