I was studying combined paging/segmentation systems and in my book there were two approaches to this :
1.paged segmentation
2.segmented paging
I could not make out the difference between the two. I think in paged segmentation the segment is divided into pages and in segmented paging the pages are divided into segments, though I don't know if I am right or wrong. Meanwhile on the internet the combined paging/segmentation is described using one scheme only. I can't figure out why in my coursebook there are two schemes for this. Any help would be deeply appreciated.
So,after vigorously searching on net for the difference or similarity between these two terms,I have come up on a final answer.First of all I would write down the similarities:
They both (segmented paging and paged segmentation) are a type of paging/segmentation combined systems (Paging and Segmentation can be combined by dividing each segment into pages).
In both the system the segments are divided into pages.
Now to describe the differences I will have to define and describe each term separately:
Segmented paging- Segments are divided into pages.Implementation requires STR(segment table register) and PMT(page map table).In this scheme, each virtual address consists of a segment number, page number within that segment and an offset within that page.The segment number indexes into segment table which yields the base address of the page table for that segment.The page number indexes into the page table,each of which entry is a page frame.Adding the PFN(page frame number) and the offset results in the physical address.Hence addressing can be described by the following function :
va = (s,p,w) where, va is the virtual address, |s| determines number of
segments (size of ST), |p| determines number of pages per segment (size of
PT), |w| determines page size.
address_map(s, p, w)
{
pa = *(*(STR+s)+p)+w;
return pa;
}
The diagram is here:
Paged Segmentation- Sometimes segment table or page table may too large to keep in physical memory(they can even reach MBs).Therefore,the segment table is divided into pages too and thus a page table of ST pages is created. The segment number is broken into page no.(s1) and page offset(s2) of page table of ST pages.So,the virtual address can be described as :
va = (s1,s2,p,w)
address_map
(s1, s2, p, w)
{
pa = *(*(*(STR+s1)+s2)+p)+w;
return pa;
}
The diagram description is here:
Best characteristics of paging
The fact is, paging has the following goodies:
Fast Allocation (At least faster than segmentation)
No External Fragmentation(The last page in this method suffers from Internal Fragmentation)
Best characteristics of segmentation
But there is also a great behavior seen from segmentation:
Sharing
Protection
The given terms, can be combined and create the following terms:
Segmented Paging: The virtual address space is divided into segments. The physical address space is divided into page frames.
Paged Segmentation: The main Segmentation Technique which uses the process segment table sometimes goes out of bound! Meaning that the size gets too large and the main memory does not have enough space to keep the segment table. Therefore the segment table and the segment number is divided into pages.
Requirements for the Segmented Paging
There are multiple steps need to be taken to achieve the Segmented Paging:
Each segment table entry represents a page table base address.
STR(Segment Table Register) and PMT(Page Map Table) are filled with desired values.
Each virtual address consists of a Segment Number, Page Number and the Offset within that page.
The segment number indexes into the segment table which gives us the the base address of the page table for that segment.
The page number indexes into the page table.
Each page table entry is a page frame.
Final result which is a Physical Address is found by adding the page frame number and the offset.
Requirements for the Paged segmentation
The following steps take place in this scheme:
Each segment entry is divided into multiple segments.
For each segment table entry, which represents a gathering of the pages, a page table is created.
Segmentation leads to slower page translations and swapping
For those reasons, segmentation was largely dropped on x86-64.
The main difference between them is that:
paging splits memory into fixed sized chunks
segmentation allows different widths for each chunk
While it might appear smarter to have configurable segment widths, as you increase memory size for a process, fragmentation is inevitable, e.g.:
| | process 1 | | process 2 | |
----------- -----------
0 max
will eventually become as process 1 grows:
| | process 1 || process 2 | |
------------------ -------------
0 max
until a split is inevitable:
| | process 1 part 1 || process 2 | | process 1 part 2 | |
------------------ ----------- ------------------
0 max
At this point:
the only way to translate pages is to do binary searches over all pages of process 1, which takes an unacceptable log(n)
a swap out of process 1 part 1 could be huge since that segment could be huge
With fixed sized pages however:
every 32-bit translation does only 2 memory reads: directory and page table walk
every swap is an acceptable 4KiB
Fixed sized chunks of memory are simply more manageable, and have dominated current OS design.
See also: How does x86 paging work?
Related
I got this question during an exam last week and I still cannot figure out how to get to the correct answer.
I think that first, the 8MiB block of data can at worst be saved on 2049 pages (8MiB/4KiB + 1 due to the data not starting at the start of a page). But that is basically all I have as I get confused and tangled up in the question every time.
How many page faults may occur at the most when copying a contiguous 8
MiB block of memory (i.e., from memory to memory) under the following
assumptions:
32-bit virtual address space, 4 KiB pages, three-level page tables
1st page table level has only 4 8-byte items, 2nd and 3rd page table levels have 512 of 8-byte items in each paging table
there is enough free frames, there will be no page replacement
the first level paging table is always in the memory
OS implements a very simple algorithm which allocates only one frame during each page failure
we do not take into account potential page faults caused by instruction fetching (we expect the code is already in the memory)
I was reading here and at the problem 3, exercise 2 he states:
The top-level page table should not assume that 2nd level page tables are page-aligned. So, we store full physical addresses there. Fortunately, we do not need control bits. So, each entry is at least 44 bits (6 bytes for byte-aligned, 8 bytes for word-aligned). Each top-level page table is therefore 256*6 = 1536 bytes (256 * 8 = 2048 bytes).
So, why does first layer can't assume page aligned 2nd layer?
Since it's presumes that the memory is not allocated in page granularity, wouldn't that make the allocation significantly more complicated?
I have tried btw to read the lectures of the course but they are that comprehensive.
We have a 1024*1024 matrix with 32 bit numbers that is going to be normalized. Suppose that the size of the page in the virtual memory is 4KB and we allocate 1 MB of main memory to save the matrix while we are working. Suppose that we need 10 ms to upload a page from the disc.
a) Suppose that we work with the matrix one column at a time. How many page faults will be caused to traverse all the matrix elements, if they are saved in the virtual memory by column?
The answer is 1024, but I don't understand why this is?
b) What if we work by row not by column?
The answer for this is 1024 page faults*2*1024
How do we get both of these answers,can you explain these to me?
Since an entry of the matrix is of size 32 bit, which is 4 Bytes, an entire row or column can be stored in a virtual memory of 4 Bytes * 1024 = 4KB. Since the memory is filled using columns, we can fit exactly one column in the memory.
Say we walk over the elements column by column. Getting the first entry we see this one is not present in the virtual memory so we have to load it (i.e. page fault). Now the entire column is stored so the next 1023 elements do not yield a page fault (they are all present in the memory). The next fault appears when accessing the first element of the second column. In general we have one page fault per column, which results in 1024 page faults.
Now we traverse the matrix row wise, every time we access the an element it will not be contained in the memory. This is clear since we have one column on the memory at all time and we never access elements of the same column sequentially. So each entry gives a page fault, resulting in 1024*1024 page faults.
(well, actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.)
I have recently started learning computer organisation and architecture. I have gained fair understanding for how caches are organised, how mapping between cache and main memory takes place (direct , fully and set-associative mapping), what is a page table(what are pages, blocks etc.), i can that say I have basic knowledge of segmentation , paging, virtual address and physical addresses.( at the basic level ofcourse).
well I have come across this question:
A computer has 46-bit virtual address ,32- bit physical address, and a three level
page table organisation. The page table base-register stores the base address of the
first level table(t1), which occupies exactly one page.Each entry of t1 stores the base
address of the page of second level table t2. Each entry of t2 stores the base address
of the page of the third level table t3. Each entry of t3 stores a page table entry
(PTE). The PTE is 32 bit in size. The processor used in the computer has a 1MB
16-way set associative virtually indexed physically tagged cache. The cache block size
is 64 Bytes.
First of all I am facing difficulty in just imagining such type of a virtual computer.
can any one help me by giving a simple steps on How to realize such a virtual computer on paper, or just how to understand what is given in the question. What is really asked??
How would one represent a computer having a 46-bit virtual address and having three level page table.
what is virtually indexed and physically tagged cache.
After reading what is given above , I feel that I just know the terms but I am unable to relate them together to solve problems.
I will be glad If someone tries to explain how my thought process should be understand and apply these concepts practically to solve such types of problems.
some questions based on the above paragraph:
1) What is the size of a page in KB in this computer?
2) what is the minimum number of page colours needed to guarantee that no two synonyms
map to different sets in the processor cache of this computer?
A good resource where such problems are actually taught to solve will a appreciated.
Good articles and views are most welcome.
Thankyou in advance !!
We know that all levels page tables must be completely full except outermost, outermost page table may occupy whole page or less. But in question it is given that Outermost page table occupy whole page.
Now let page size is 2 Bytes.
Given that PTE = 32 bits = 4 Bytes = 22 Bytes.
Number of entries in any page of any pagetable =page size/PTE = 2p/22 = 2p-2.
Therefore Logical address split is
|---------------------|------------------|---------------------|-------------|
| p-2 | p-2 | p-2 | p |
|---------------------|------------------|---------------------|-------------|
logical address space is 46bits given.
Hence equation becomes,
(p-2)+(p-2)+(p-2)+p = 46
⇒p=13.
There fore page size is 213 Bytes =8KB.
I can help you with the first question.
Let page size is 2^x. Each entry of T1 is 32 bits means 4 bytes. Total size is 2^X bytes(1 page). T1 contains 2^X / 4 = 2^(X-2) entries.
So we use first X-2 bits of the 46 bit virtual address to index into one entry in T1. It gives the address of one T2.
T2 also contains 2^(X-2) entries.( same way as T1). So we use next X-2 bits to index into T2 and get the address of a T3.
It is given each entry of T3 is 32 bytes (including flags and all). Total size of 1 page = 2^X bytes. No of entries is 2^(X-2). So again we use X-2 bits to index into T3 and get the staring adress of frame.
Then we need the offset. Since the page size is 2^X, offset is X bits long.
First (x-2) bits gives address of T2.
Next (x-2) bits gives address of T3.
Next (x-2) bits gives address of Frame from T3.
Remaining x bits give offset in frame.
Total is 46 bits
x-2 + x-2 + x-2 + X = 46
4X - 6 = 46
X =13
Page Size = 2^13 bytes.
Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.