We have a 1024*1024 matrix with 32 bit numbers that is going to be normalized. Suppose that the size of the page in the virtual memory is 4KB and we allocate 1 MB of main memory to save the matrix while we are working. Suppose that we need 10 ms to upload a page from the disc.
a) Suppose that we work with the matrix one column at a time. How many page faults will be caused to traverse all the matrix elements, if they are saved in the virtual memory by column?
The answer is 1024, but I don't understand why this is?
b) What if we work by row not by column?
The answer for this is 1024 page faults*2*1024
How do we get both of these answers,can you explain these to me?
Since an entry of the matrix is of size 32 bit, which is 4 Bytes, an entire row or column can be stored in a virtual memory of 4 Bytes * 1024 = 4KB. Since the memory is filled using columns, we can fit exactly one column in the memory.
Say we walk over the elements column by column. Getting the first entry we see this one is not present in the virtual memory so we have to load it (i.e. page fault). Now the entire column is stored so the next 1023 elements do not yield a page fault (they are all present in the memory). The next fault appears when accessing the first element of the second column. In general we have one page fault per column, which results in 1024 page faults.
Now we traverse the matrix row wise, every time we access the an element it will not be contained in the memory. This is clear since we have one column on the memory at all time and we never access elements of the same column sequentially. So each entry gives a page fault, resulting in 1024*1024 page faults.
Related
I got this question during an exam last week and I still cannot figure out how to get to the correct answer.
I think that first, the 8MiB block of data can at worst be saved on 2049 pages (8MiB/4KiB + 1 due to the data not starting at the start of a page). But that is basically all I have as I get confused and tangled up in the question every time.
How many page faults may occur at the most when copying a contiguous 8
MiB block of memory (i.e., from memory to memory) under the following
assumptions:
32-bit virtual address space, 4 KiB pages, three-level page tables
1st page table level has only 4 8-byte items, 2nd and 3rd page table levels have 512 of 8-byte items in each paging table
there is enough free frames, there will be no page replacement
the first level paging table is always in the memory
OS implements a very simple algorithm which allocates only one frame during each page failure
we do not take into account potential page faults caused by instruction fetching (we expect the code is already in the memory)
I'm studying operating systems and I have a question about page tables.
I came across this question where it asks how the page table size and entry size changes when the size of the page changes. Say the size of a page is reduced from 8KB to 4KB. Now, my guess is that the size of the page table will be doubled, because now the paging system needs twice as more entries to map the pages to frames.
But for the size of the page table entry, I am not so sure. My guess is that the page table entry will be smaller because the physical address it contains is shorter. This is because the physical address is determined by the page/frame size, and if the page size is smaller, the length of the physical address will be 2^-1 shorter as well.
But is this a good assumption? Is the size of the page table entry determined by the length of the address? Or, is the entry size fixed, regardless of the size of each frame/page? I can't seem to find resources / questions specifically regarding the entries.
Thank you!
I'll try to answer to your example, i.e., reducing the page size from 8KB to 4KB. In that case, as you said, the total number of PTEs (page table entries) is indeed doubled, because the number of pages in the virtual address space is doubled.
For the PTE size: the PTE contains several fields, the most important of them is obviously the frame number, which points to the physical address in which the corresponding page lies. Smaller pages also means smaller frames and longer frame numbers, because the number of bits required to represent a frame number is $log2(physical address space size / frame size)$.
So does it mean that we would have larger PTEs? Not necessarily.
As many other architectural structures, the PTE size is rounded up to the nearest power-of-two. On x86-64 CPUs, e.g., the PTE size is 64 bits, but only 48--52 of them are actually in use. So adding a few bits (only one in your example) to the frame number field would probably leave the PTE size unchanged.
Edit: you can see the PTE structure in the x86-64 architecture here:
https://qph.ec.quoracdn.net/main-qimg-0bcd46d62af1b35820a88f7afc4a50de
(taken from https://www.quora.com/How-is-a-page-walk-implemented )
I am not able to understand the difference between Page Size and Page Table Entry size.
From my understanding, Page size is used to divide the Page table in equal no. of blocks called Pages and the same size is used to divide the main memory into frames.
Page Size = Frame Size.
Sorry for poor drawing skills. This is my visualization of the Page Table
Where as Page Table Entry Size is the size occupied by the each page entry. So,
Page Table Entry Size = Page Size.
But Page Table entry size is calculated by the number of bits in the frame number.
Can anyone please explain how Page Size differs from Page Table Entry size?
Why Page Table Entry size is calculated basing on No. of bits in the frame instead of the page?
Please help me visualize how exact the page table will be with all the above components
Why Page Table Entry size is calculated basing on No. of bits in the frame instead of the page?
The PAGE FRAME size is always the same as the PAGE size.
Can anyone please explain how Page Size differs from Page Table Entry size?
The PAGE TABLE ENTRY Size is dependent upon the PAGE size but is not calculated rom it.
A PAGE TABLE is a data structure that defines the logical address space of a process. A process address space consists of a set of PAGES. The size of a page can be any multiple of 2. The smallest page size I have seen is 512 bytes and the largest can be megabytes (or possibly gigabytes).
A PAGE TABLE is composed of PAGE TABLE ENTRIES. A PAGE TABLE ENTRY describes a single page in the process's logical address space. A PAGE TABLE ENTRY identifies the physical page frame that the logical page maps to and the attributes of the page.
A PAGE TABLE ENTRY then requires some number of bits to describe the page and some number of bits to maps the page to a physical page frame.
PAGE TABLE ENTRIES are always powers of 2 in size and are typically 4, 8, or 16 bytes long. Thus PAGE sizes are orders of magnitude larger than PAGE TABLE ENTRIES sizes.
The number of bits used to map PAGE to PAGE FRAMES is
maximum amount of physical memory / page size
Larger physical memory support => larger page table entries.
Larger PAGE size => smaller page table entries.
If a system wants to support 2^32 bytes of memory using 512 (2^9) byte PAGES, it needs 2^23 bits in a PAGE TABLE ENTRY to map logical pages to physical page frames. That would leave 9 bits for PAGE description in a 32-bit PAGE TABLE ENTRY.
"Page Size = Frame Size"
This is correct.
Physical memory divided into chunks called "page-frames".
Virtual memory divided into chunks called "pages".
PTE contains the base address of a page-frame and based on the offset we decide the actual address.
Refer to Understanding the Linux kernel Ch. 2 memory addressing.
Explained here in Fig-3.1
1)A Page size is given by the designer and page size=frame size
2)A frame size specifies size of each chunk by which main memory is divided.
3)The content that each page stores is an address of a frame, where in main memory is a particular frame is present.
4)Then the content you store in each page contains number of bits required to address a frame uniquely i.e (size of main memory/size of each page)
-->Let us consider an example.
Let Physical address be 44 bit long
Let Logical address a CPU generates be 32 bit long
Let Size of each page be 4KB(12 bits)
There are (2^44)/(2^12) frames in main memory
As page size== frame size
we need 44-12=32 bits to identify each frame uniquely
So each page in page table must be capable of storing 32 bits. This is called size of a page table entry
We know that Page size is equal to Frame size. Now, since page table represents the FRAMES corresponding to the page, then the number of bits required for page table entry should be equal to total number of bits required to represent frame number because a page can be anywhere in the main memory.
(well, actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.)
I have recently started learning computer organisation and architecture. I have gained fair understanding for how caches are organised, how mapping between cache and main memory takes place (direct , fully and set-associative mapping), what is a page table(what are pages, blocks etc.), i can that say I have basic knowledge of segmentation , paging, virtual address and physical addresses.( at the basic level ofcourse).
well I have come across this question:
A computer has 46-bit virtual address ,32- bit physical address, and a three level
page table organisation. The page table base-register stores the base address of the
first level table(t1), which occupies exactly one page.Each entry of t1 stores the base
address of the page of second level table t2. Each entry of t2 stores the base address
of the page of the third level table t3. Each entry of t3 stores a page table entry
(PTE). The PTE is 32 bit in size. The processor used in the computer has a 1MB
16-way set associative virtually indexed physically tagged cache. The cache block size
is 64 Bytes.
First of all I am facing difficulty in just imagining such type of a virtual computer.
can any one help me by giving a simple steps on How to realize such a virtual computer on paper, or just how to understand what is given in the question. What is really asked??
How would one represent a computer having a 46-bit virtual address and having three level page table.
what is virtually indexed and physically tagged cache.
After reading what is given above , I feel that I just know the terms but I am unable to relate them together to solve problems.
I will be glad If someone tries to explain how my thought process should be understand and apply these concepts practically to solve such types of problems.
some questions based on the above paragraph:
1) What is the size of a page in KB in this computer?
2) what is the minimum number of page colours needed to guarantee that no two synonyms
map to different sets in the processor cache of this computer?
A good resource where such problems are actually taught to solve will a appreciated.
Good articles and views are most welcome.
Thankyou in advance !!
We know that all levels page tables must be completely full except outermost, outermost page table may occupy whole page or less. But in question it is given that Outermost page table occupy whole page.
Now let page size is 2 Bytes.
Given that PTE = 32 bits = 4 Bytes = 22 Bytes.
Number of entries in any page of any pagetable =page size/PTE = 2p/22 = 2p-2.
Therefore Logical address split is
|---------------------|------------------|---------------------|-------------|
| p-2 | p-2 | p-2 | p |
|---------------------|------------------|---------------------|-------------|
logical address space is 46bits given.
Hence equation becomes,
(p-2)+(p-2)+(p-2)+p = 46
⇒p=13.
There fore page size is 213 Bytes =8KB.
I can help you with the first question.
Let page size is 2^x. Each entry of T1 is 32 bits means 4 bytes. Total size is 2^X bytes(1 page). T1 contains 2^X / 4 = 2^(X-2) entries.
So we use first X-2 bits of the 46 bit virtual address to index into one entry in T1. It gives the address of one T2.
T2 also contains 2^(X-2) entries.( same way as T1). So we use next X-2 bits to index into T2 and get the address of a T3.
It is given each entry of T3 is 32 bytes (including flags and all). Total size of 1 page = 2^X bytes. No of entries is 2^(X-2). So again we use X-2 bits to index into T3 and get the staring adress of frame.
Then we need the offset. Since the page size is 2^X, offset is X bits long.
First (x-2) bits gives address of T2.
Next (x-2) bits gives address of T3.
Next (x-2) bits gives address of Frame from T3.
Remaining x bits give offset in frame.
Total is 46 bits
x-2 + x-2 + x-2 + X = 46
4X - 6 = 46
X =13
Page Size = 2^13 bytes.
Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.