I have a clock of 100 mhz. I want to use DCM to create a clock of 78 mhz.
I think I should use two DCM, where the output of first DCM goes into the second DCM but I don't know if this will work.
Best Regards
Rather than using a DCM directly you can investigate using a Direct Digital Frequency Synthesizer (DDFS). It amounts to an accumulator that is incremented by a constant count value. You can control the precision by the size of the accumulator.
It is helpful if there is as much disparity between the accumulator clock and the generated frequency as possible. Consider using a DCM to scale the 100MHz up to the highest speed you can run a counter of the necessary width and still meet timing for your target device. There will be some jitter equal to one period of whatever clock is driving the accumulator but the average frequency can be made very close to 78 MHz.
accum_freq = 100 MHz * DCM_MULTIPLIER
accum_size = ceil(log2(accum_freq / (78 MHz * tolerance)))
increment = 78 MHz / accum_freq * 2**accum_size
accum = accum + increment
You then tap off the MSB of the accumulator to get your synthesized 78 MHz clock.
You can either manually compute these constants for use as magic numbers or do the arithmetic natively in VHDL to define the size and increment as machine computed constants. By reducing the tolerance you will increase the required size of the accumulator. Start off with 0.01% (0.0001) and see if it is satisfactory.
What device are you targeting? On a Spartan-6 the DCM_CLKGEN allows a multiplier of 39 and a divider of 50, which gets you your 78MHz.
If you set your multiplier to 7 and your divider to 9 you'll be able to get to 77.77 MHz. Will that work for you?
Related
My design uses an Xilinx FPGA.
The synthesis report shows the following results:
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: 1.903ns
Maximum output required time after clock: 150.906ns
Maximum combinational path delay: 97.819ns
I do not know if I should use 150.906 ns or 97.819 ns to calculate throught.
What is maximum clock delay?
I havn't heard the term 'throught' with respect to circuit timing anytime before, but maybe my explanantion will give you the right hint.
At first, the maximum clock delay can be found in the Static Timing Report after Place & Route. But, this figure is mostly meaningless because one must also take the maximum data delay from any input or to any output into account. The result is already provided by the synthesis report. Please note, that this report only provides estimated results. Real results are only available from the Static Timing Report.
If you look for the maximum clock frequency (the inverse of the minimum clock period), then your synthesis report states, that your design does not include a path from one FF to another driven by the same clock ("Minimum period: No path found").
If you want to synchronously communicate with another IC on your PCB then the other 3 numbers are relevant. For example, the line "maximum output required time after clock" states that, all output signals are valid 151 ns after the clock signal toggles at the input pin (rising or falling edge depending on your design). If any of this outputs drive the inputs of another IC and if this IC is driven by the same clock source, then you must add the "minimum input arrival time" of this second IC (found in its data sheet). If this time is for example 49 ns then, the minimum period of your shared clock would be (your) 151 ns + 49 ns = 200 ns, that would be 5 MHz.
Same applies for the "minimum input arrival time before clock" of your FPGA design which must be added to the "maximum output required time" of the driving IC. If this time is for example 31 ns, then the minimum period of your shared clock would be 31 ns + (your) 2 ns = 33 ns, that would be 30 MHz.
In the same way, the "maximum combinational path delay" must be added to the "maximum output required time" of the IC which drives your inputs plus the "minimum input arrival time" of the IC your FPGA is driving. Given the same example figures from above, then the minimum period of your shared clock would be 31 ns + (your) 98 ns + 49 ns = 178 ns, that would be 5.6 MHz.
More details are explained in Xilinx Timing Constraint User Guide. Above, I explained the System Synchronous mode.
A more compact representation for Xilinx Vivado is given in Vivado Design Suite User Guide - Using Constraints.
There was also this presentation earlier available on the internet, but I didn't find the source PDF anymore.
I'm trying to synthetize any simple project in ISE for Spartan 6.
When I use Clocking Wizard for clk generator with f = 40 MHz (100Mhz external oscillator), XST says:
Timing Summary:
Speed Grade: -3
Minimum period: 9.482ns (Maximum Frequency: 105.458MHz)
Minimum input arrival time before clock: 2.623ns
Maximum output required time after clock: 3.597ns
Maximum combinational path delay: 5.194ns
OK, but when I change clk frequency in core generator to 100MHz, the response is Maximum Frequency is about 47MHz ...
What is wrong?
What is the right way to determine max frequency?
The reported maximum frequency in synthesis is only a rough estimation based on fanout, LUT levels, i/o-buffers, ...
The real timing analysis is done after Place & Route.
I have a project which already utilizes synthesis timing constraints (additional xcf-file), were XST reports f_max = 82 MHz. After P&R the design achieves 152 MHz :)
I need to divide the 50 MHz clock to 1.5 Mhz with 50% duty cycle using VHDL. For that I wanted to use a counter to count the number of 50 Mhz clock pulses until half of the 1.5 Mhz clock period i.e 16.6666 which is in decimal which I don't know how to implement in the code. Can any one please help me with it?
Thank you very much.
I'm not an expert in VHDL but I don't think you can get exactly to 1.5 MHz with synthesizable code. You could maybe get an average of 1.5 MHz if you vary how many clock cycles you wait on the 50 MHz clock until you raise the 1.5 MHz one.
If you only want code that can be simulated then of course you can just use arbitrary delays.
The approach you are suggesting will result in an approximation, which may of course be ok. If not, I would suggest you use instantiate a PLL or clock manager specific to the target technology.
I have implemented a frequency divider by the powers of 2. Now I am interested in doing a divider by any integer number from 1 to 16. Yes, I have tried but yet no ideas. How can I approach this problem?
I want to use common elements like multiplexers, flip flops and so on. Not asking for a complete solution, even though it would be great.
That is normally the job of a PLL many FPGA have some PLL on chip.
Or try a counter that resets when limit (0-15) is reached.
Each time limit is reached toggle clock.
The value for 1:1 clock needs special handling, maybe a clock bypass.
A better way would be to run the counter at double frequency to avoid the mux.
Instead of an incrementing counter a decrementing counter that loads the configured value on zero would do as well.
I need to create a VHDL code for this situation:
**Draw a control circuit that generates a pulse signal with:
fixed working frequency (100 KHz)
variable working cycle
The phase difference should be increased or decreased by the direction of the spin of a rotary control of 8 bits.**
Additional info:
D = t (on) / T
D = working cycle
t (on) = Time the activated signal lasts (rotary control of 8 bits)
T = signal period (constant)
You seem to be wanting to generate a mark:space ratio of between 1:255 and 255:1, so you will need a clock frequency of 256 * 100kHz.
An 8 bit incrementing counter can be left free-running clocked at that rate.
Now have a flop that is SET when the counter overflows from X'FF to X'00 and that CLEARS when the timer value makes the transition from N-1 to N. Where N is the 8 bit value on your duty cycle setting control and controls the width of the mark.
The threshold controlled flop's output is your variable duty cycle 100kHz.