Suppose I have these following c++ files, how should I write a basic makefile for them (using g++)?
a.cpp a.h, b.cpp b.h, c.cpp c.h, main.h
When b.h includes a.h, c.h includes b.h and main.h includes c.h?
thanks a lot
so you can write.
EXE := exe
CC := g++
CPP_FILES := a.cpp b.cpp c.cpp
HPP_FILES := a.h b.h c.h main.h
$(EXE) : $(CPP_FILES) $(HPP_FILES)
$(CC) -o $# $(CPP_FILES)
.PHONY : clean
clean:
rm -rf $(EXE) *.o
How to compile a file? Say you have test.cpp and test.h now, to compile and link it:
g++ -c test.c
g++ -o test test.o
Easiest Makefile:
test: test.o #means test depends on test.o
g++ -o test test.o
test.o: test.cpp test.h #means test.o depends on test.cpp and test.h
g++ -c test.cpp
#if you want clean? add below line too.
clean:
rm test test.o
If your app depends on multiple files, then
test: test1.o test2.o test3.o #means your app depends on test1.o test2.o and test3.o
g++ -o test test1.o test2.o test3.o
test1.o: test1.cpp test1.h
g++ -c test1.cpp
test2.o: test2.cpp test2.h
g++ -c test2.cpp
...
Related
I want to add -std=c++11 to my makefile but I do not Where to add, here is my code:
hw07: test.o functions.o
g++ test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -c functions.cpp
clean:
rm *.o hw07
in the above code where should I add the stdc++11 code, please help me out about...
Instead of spelling out all of the rules and all of the commands, use variables and implicit rules to build your program:
CXXFLAGS = -std=c++11
hw07: test.o functions.o
test.o: test.cpp headerfile.h
functions.o: functions.cpp headerfile.h
clean:
rm *.o hw07
This will have make build the object files using $(CXXFLAGS) as the options to pass to the compiler. Then make will build the program hw07 using the files listed in its dependencies.
Other flags that are good to have when compiling the source files are -Wall and -Wextra. Those enable more warning messages from the compiler, that in almost all cases point out suspect things that could lead to problems.
You can just add -std=c++11 after each g++:
hw07: test.o functions.o
g++ -std=c+++11 test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -std=c+++11 -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -std=c+++11 -c functions.cpp
clean:
rm *.o hw07
Also you can use a variable:
CPP_FLAGS='-std=c++11'
hw07: test.o functions.o
g++ ${CPP_FLAGS} test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ ${CPP_FLAGS} -c test.cpp
functions.o: functions.cpp headerfile.h
g++ ${CPP_FLAGS} -c functions.cpp
clean:
rm *.o hw07
Suppose we have a.c b.c c.c .So the make file will like this
app: a.o b.o c.o
gcc -o app.o a.o b.o c.o
a.o: a.c
gcc -c a.c
b.o: b.c
gcc -c b.c
c.o: c.c
gcc -c c.c
In the future more C files may be added. So do I need to make target of .o extensions for each .c file. I got to know about suffix rules which uses the .source-extension.target-extension. But I could understand how to use this suffix rule in the make file. Please provide me the command to be included in make file and please describe the syntax.I am newbie to makefile.
You can use the below makefile.
app: a.o b.o c.o
gcc -o $# $^
a.o : a.h
b.o : b.h
c.o : c.h
%.o: %.c
gcc -c $<
Where $# is the target(app), $^ is the list of dependencies and $< is the corresponding c file to compile to object file
Below is the sample makefile for compiling c code.
TARGET = a.out
SRCS = a.c b.c c.c
OBJS = $(SRCS:.c=.o)
CFLAGS = -g -ggdb -O2 -Wall -Werror
CC = gcc
RM = rm
.PHONY: all clean
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
$(TARGET) : $(OBJS)
$(CC) $^ -o $#
clean:
$(RM) *.o
$(RM) $(TARGET)
I assume most of you will think I did not try to search on the internet by myself but I really did. I understand nothing on makefile and I tried to create one for c++.
I have only two files: Set.hpp and main.cpp.
Here is my wrong makefile.
CC=g++
CFLAGS= --std=c++0x --pedantic -g -Wall -W
LDFLAGS=
EXEC=main
all: $(EXEC)
main: Set.o main.o
$(CC) -o main Set.o main.o $(LDFLAGS)
main.o: main.cpp
$(CC) -o main.o -c main.cpp $(CFLAGS)
Set.o: Set.hpp
$(CC) -o Set.o -c Set.hpp $(CFLAGS)
clean:
rm -rf *.o
mrproper: clean
rm -rf $(EXEC)
The error I get is simply Make: * no targets. Stop.. I really need help for this please :/ Thank you in advance :)
.hpp files are header files. They are NOT to be complied. They are to be included in the source file. You can find more about the .hpp files and some related info here.
Now, to start with a "working" version of your makefile, let's consider the following points. I assume you have two source files
1. main.cpp
2. Set.cpp
and one header file
1. Set.hpp
in the same directory. Please consider the sample files provided below.
main.cpp
#include <iostream>
#include "Set.hpp"
using namespace std;
int main()
{
call_func();
cout <<"And this is from main.cpp"<<endl<<endl;
return 0;
}
Set.cpp
#include <iostream>
#include "Set.hpp"
using namespace std;
int call_func()
{
cout<<"This is from set.cpp"<<endl<<endl;
return 0;
}
Set.hpp
#include <iostream>
using namespace std;
int call_func();
Makefile
CC=g++
CFLAGS= --std=c++0x --pedantic -g -Wall -W
LDFLAGS=
EXEC=main
all: $(EXEC)
main: Set.o main.o
$(CC) -o main Set.o main.o $(LDFLAGS)
main.o: main.cpp
$(CC) -o main.o -c main.cpp $(CFLAGS)
Set.o: Set.cpp # notice the change from .hpp to .cpp
$(CC) -o Set.o -c Set.cpp $(CFLAGS) # notice the change
clean:
rm -rf *.o
mrproper: clean
rm -rf $(EXEC)
After that, the output is like
[sourav#infba01383 so_overflow]# make
g++ -o Set.o -c Set.cpp --std=c++0x --pedantic -g -Wall -W
g++ -o main.o -c main.cpp --std=c++0x --pedantic -g -Wall -W
g++ -o main Set.o main.o
[sourav#infba01383 so_overflow]# make
make: Nothing to be done for `all'.
[sourav#infba01383 so_overflow]# make clean
rm -rf *.o
[sourav#infba01383 so_overflow]#
Hope this helps!!!
I have this file:
main.c
A.h
A.c
B.h
B.c
X.h
and in main.c I include A and in A.h I include B and in B.h I include X.h
How could I write makefile for this? please tell me about dependency diagram of this example
Try this:
main: main.o A.o B.o
gcc -o main main.o A.o B.o
%.o: %.c
gcc -c $<
While compiling the .c files you don't have to worry about dependencies yet, only when linking the executable.
Lets say I have files:
Libs:
one.cpp, one.h
two.cpp, two.h
three.cpp, three.h
Program:
program.cpp
Is there way, to create Makefile which will compile only that *.cpp which were modified from last compilation?
Currently I have something like that:
SRCS = one.cpp two.cpp three.cpp
OBJS = $(SRCS:.cpp=.o)
all: $(OBJS) program
.cpp.o:
g++ -Wall -c $<
program:
g++ -Wall $(OBJS) program.cpp -o program
clean:
rm -f $(OBJS) program
I works fine, but when I compile my program and then change two.cpp or two.h I need to run "make clean" first, because when I secondly run "make" I get:
Nothing to be done for 'all'.
I would like to change my Makefile in that way, it would recognize my changes and recompile that file and its dependencies (if one.cpp uses code from two.cpp which was modified, both files should be recompiled).
So if I modify two.cpp, make should do:
g++ -Wall -c two.cpp
g++ -Wall $(OBJS) program.cpp -o program
But if one.cpp uses code from two.cpp which was modified, make shold do:
g++ -Wall -c one.cpp
g++ -Wall -c two.cpp
g++ -Wall $(OBJS) program.cpp -o program
First we make the object files prerequisites of the executable. Once this is done, Make will rebuild program whenever one of the SRCS changes, so we don't need OBJS as an explicit target:
all: program
program: $(OBJS)
g++ -Wall $(OBJS) program.cpp -o program
Then we make the header files prerequisites of the objects, so that if we change three.h, Make will rebuild three.o:
$(OBJS): %.o : %.h
And finally since one.cpp uses code from two.cpp by means of two.h (I hope), we make two.h a prerequisite of one.o:
one.o: two.h
And to make things cleaner and easier to maintain we use automatic variables:
program: $(OBJS)
g++ -Wall $^ program.cpp -o $#
Put it all together and we get:
SRCS = one.cpp two.cpp three.cpp
OBJS = $(SRCS:.cpp=.o)
all: program
$(OBJS): %.o : %.h
one.o: two.h
.cpp.o:
g++ -Wall -c $<
program: $(OBJS)
g++ -Wall $^ program.cpp -o $#
clean:
rm -f $(OBJS) program
There are a few more things we could do (like adding program.o to OBJS), but this is enough for today.
Add the files a command depends upon to run to the right of the target name.
Example:
default: hello.c
gcc -o hello.bin hello.c
install: hello.bin
cp hello.bin ../
All you need to do is tell make that the .o file depends on the .cpp file:
%.cpp.o: %.cpp
g++ -Wall -c -o $# $<