When trying to assemble the system according to the instructions in this document
http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf
I get this error message:
Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.nios2_qsys_0.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2_qsys_0.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must declare an associated reset
Warning: System.leds.reset: Interface has no signals
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver
Can you tell me what is wrong?
Since the document uses SOPC Builder, you would need to make certain changes so that it works with QSys without errors.
I have listed the fixes for the errors in your question below:
Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0
not connected to instruction_master.
Fix: Connect avalon_slave_0 of the sram to the instruction_master of the nios2_qsys processor.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Fix: Edit the de2_sram_controller.vhd file and add the following lines to the signal declarations:
signal clk: in std_logic;
signal reset_n: in std_logic;
Then, edit the sram component you created in QSys and add the clk and reset_n signals.
Error: System.nios2_qsys_0.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2_qsys_0.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Fix: In the QSys window, go to System --> Assign Base Addresses.
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must
declare an associated reset
Fix: Edit the sram and led components. Under the Interfaces tab make sure Associated Reset has a reset signal (shown in the image below).
Warning: System.leds.reset: Interface has no signals
Fix: Edit the led component. Under the Interfaces tab, towards the bottom, click Remove Interfaces With No Signals.
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.
Fix: In the QSys window, for both the sram and led components, under the Export column, ensure you Double-click to export.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver
Fix: Ensure that the avalon_jtag_slave of the jtag_uart_0 is connected to IRQ 31. Refer to the image below and double-click the white circle connecting the jtag_uart_0 to IRQ 31.
I hope this helps.
There is a problem with the sram custom component. It only has a conduit and an Avalon-slave interface, its reset and clock inputs are not visible since the declaration of the component itself is apprently incomplete.
These problems could possibly be fixed by editing the custom component. Right-click the sram component (left pane), Edit -> Interfaces (tab), make sure each interface has a clock and a reset assigned. Once done, generate the component with a new version number, and in Qsys upgrade the component to the edited version (System -> Upgrade IP cores...). Then make sure to connect the clock and reset ports for the sram which should now be visible in Qsys.
There are similar problem with the leds custom component.
It is possible or probable that the above problems are due to trying to use components for SOPC Builder in Qsys
There are also problem with overlapping base adresses. This can be fixed by System -> Assign Base Adresses.
There is an unconnected interrupt as well - scroll right in Qsys so you see the Interrupts column and connect the interrupt between the JTAG UART to the Nios processor.
Related
I am busy getting some hands on experience using Xilinx Vivado.
Taking a VHDL sine generator from github (https://github.com/jorisvr/vhdl_sincos_gen) I made an IP package out of it. I defined the ports:
So the 'in_phase' port is of type unsigned.
After packaging the IP I created a new project with a block design and instantiated the IP:
This works and I can synthesize the design. Simulation however fails. I get the following errors in the elaboration log:
Starting static elaboration
ERROR: [VRFC 10-619] entity port in_phase does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:80]
ERROR: [VRFC 10-619] entity port out_sin does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:81]
ERROR: [VRFC 10-619] entity port out_cos does not match with type std_logic_vector of component port [/home/dinne/Xilinx/projects/nexys4ddr_tst/nexys4ddr_tst.ip_user_files/bd/design_1/ip/design_1_sincos_gen_0_0/sim/design_1_sincos_gen_0_0.vhd:82]
Somehow the port types are changed. If I check the port properties of for example the "in_phase" port I see that the type is "undef".
Also If I check the generated IP wrapper code I see that the port types have changed. Again the 'in_phase' port should be unsigned, but is "std_logic_vector".
How to fix the IP port types and get the simulation to run?
Vivado only allows ports of types std_logic or std_logic_vector for custom IPs. Details can be found here. Under the section Top-Level HDL Requirements, on Page 12 in this document they clearly mention:
Regardless of the top-level port type, when you synthesize the IP out-of-context (OOC), the resulting IP netlist ports are converted to std_logic or std_logic_vector. The converted netlist ports could cause type mismatch issues with RTL simulation. For Verilog, module declarations with complex or split ports are not supported.
And in the same document, on page 63, under the section Ports and Interfaces:
° Type Name: The port type (std_logic or std_logic_vector).
As each custom-IP is considered as a top level entity, using unsigned type in the top port is unfortunately not supported.
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
control_fixed_location
control_read_base
control_read_length
The interface description is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Attached is the quartus archive. Maybe someone can give me an example to simulate this interface in ModelSim.
Thanks in advance!
I have an answer to your second question. I am struggling myself with the first question.
Where can I find the base address for the ADC implemented in QSYS?
I know two methods to find the base and end address of a component.
One is to open the System Contents view (standard) and scroll to the right side .
I am not permited to embed images yet.
There you see a row named Base and End. Here you can find the addresses.
The second method is to open the Address Map. Should be located in the same column as System Contents, or you can select View in the top left corner and select it there.
Have a look. You should be able to find it yourself with this information.
What i use when i am searching for examples or prebuild designs is the altera website. Here a link for you https://cloud.altera.com/devstore/platform/
Probably you like this one: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_adc.pdf
The configuration is complete in QSYS? Like selecting channels and Sequencer in your ADC Block. Selecting the right input clocks and the right frequencies?
You wrote:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Have you created a clock for your PLL? When i want to simulate a clock signal for a QSYS system i export the clock signals and define the wanted clock in an additional file.
When you go one step further and include a nios2 processor i recommend to have a look at the altera_modular_adc.c file.
*edit
If you haven't assigned any base addresses there is a function in QSYS which does the job for you.
In System (Same column as File) -> Assign Base Addresses
Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL.
Investigating a bit further I tried to load just the PLL in modsim and I get the following error.
** Error: (vsim-3039) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/PLL1.vhd(49): Instantiation of 'PLL1_altpll_0' failed.
Region: /pll1
Error loading design
Of the 4 modules seen in the PLL1 entity see below:
Modsim will only except the bottom two. The "pll1_altpll_0" and "pll1_altpll_0_altpll_4242" modules display
Loading PLL1.PLL1_altpll_0_dffpipe_l2c
Loading PLL1.PLL1_altpll_0_altpll_4242
** Error: (vsim-3033) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/submodules/PLL1_altpll_0.v(192): Instantiation of 'cycloneiii_pll' failed. The design unit was not found.
When opened within modsim.
Has anyone had a similar problem or know where I am going wrong using either Modsim or Qsys?
Many Thanks D
Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.
Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found".
Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" : mm_slave."
I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.
So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?
I have some ideas but don't like them:
Add MM-Slave for each irq (it looks like waste of resources).
Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do?
I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.
Merge all interrupts into one wire (they all will share the same priority).
Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers.
After Component Editor stage is finished Qsys doesn't accept such a system.
Please help.
At last, I have found the following:
A. If you need many IRQ Senders inside one custom Qsys module you need one MM-Slave per each. From GUI organization it seems that you are assigning MM-Slave to the IRQ, but (as far as I understand it) it works directly opposite: IRQ is tied to MM-Slave and it may has maximum one IRQ. I didn't try to actually run it, but BSP files looks correct and everything compiles at least.
I hope, that there is (or will be) a better way to achieve this.
B. If you can share the same priority between all interrupts, than you can avoid the problem by using only 1 Interrupt Sender and thus only 1 MM-Slave. It works on dev board.
I am trying to re-use netlists in other designs without the success.
I have a component which is translated to the netlist:
entity c is
port (... sel : in std_logic_vector(31 downto 0); ... );
In the design I am using just sel(4 downto 0).
The synthesis tools notices this behaviour and gives a warning:
'WARNING:Xst:647 - Input sel<31:5> is never used ..
I am generating netlist with properties:
keep hierarchy = true
add I/O buffers = off
Whenever I want to instantiate this netlist as an black-box module in other circuit I got an error:
ERROR:NgdBuild:76 - cannot be merged into block because one or more pins on the block, including pin "sel<31>", were not found in the file.
How can I preserve the size of sel?
I should mention that the sel needs to be 32bits width since it's connected to the bus.
You could try driving the unused input ports to zero.
Can you use the component directly instead of as a pre-synthesised black-box?
You may get things to work by putting a KEEP attribute (see your synth tools manual) on the port. I've only ever tried this on signals, but it may work.
This sort of task is often described as "pushing on the rope" of the synthesiser, as it's such a pain to get it to not be as celever as it wants to be (and then in the next release of tools you need a different attribute :)