In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
control_fixed_location
control_read_base
control_read_length
The interface description is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Attached is the quartus archive. Maybe someone can give me an example to simulate this interface in ModelSim.
Thanks in advance!
I have an answer to your second question. I am struggling myself with the first question.
Where can I find the base address for the ADC implemented in QSYS?
I know two methods to find the base and end address of a component.
One is to open the System Contents view (standard) and scroll to the right side .
I am not permited to embed images yet.
There you see a row named Base and End. Here you can find the addresses.
The second method is to open the Address Map. Should be located in the same column as System Contents, or you can select View in the top left corner and select it there.
Have a look. You should be able to find it yourself with this information.
What i use when i am searching for examples or prebuild designs is the altera website. Here a link for you https://cloud.altera.com/devstore/platform/
Probably you like this one: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_adc.pdf
The configuration is complete in QSYS? Like selecting channels and Sequencer in your ADC Block. Selecting the right input clocks and the right frequencies?
You wrote:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Have you created a clock for your PLL? When i want to simulate a clock signal for a QSYS system i export the clock signals and define the wanted clock in an additional file.
When you go one step further and include a nios2 processor i recommend to have a look at the altera_modular_adc.c file.
*edit
If you haven't assigned any base addresses there is a function in QSYS which does the job for you.
In System (Same column as File) -> Assign Base Addresses
Related
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
I have a Xilinx Zybo board. I followed the instructions here and created a custom multiplier over the AXI bus. The multiplier shown on the website processes one input and generates one output. How can I modify it such that it can process streaming inputs sort of like a pipeline. Any hints?
In the tutorial, at Step 5 of "Create the custom IP", select AXI Stream interface rather than AXI Lite. Then modify the HDL source to have the proper signals for a streaming interface (mainly VALID, READY, and DATA). Then follow the rest of the steps to add the IP into your design in Vivado.
Note you'll have to create 2 streaming interfaces, one for input and one for output. Unlike AXI Lite where you can read/write a single register, a Stream is a one-directional flow of data.
EDIT: this doesn't address the way you'd test/stim from the SW side. The example will only work with an AXI Lite interface. You'd need a custom driver to work with the Streaming IF(s)
Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.
Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found".
Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" : mm_slave."
I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.
So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?
I have some ideas but don't like them:
Add MM-Slave for each irq (it looks like waste of resources).
Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do?
I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.
Merge all interrupts into one wire (they all will share the same priority).
Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers.
After Component Editor stage is finished Qsys doesn't accept such a system.
Please help.
At last, I have found the following:
A. If you need many IRQ Senders inside one custom Qsys module you need one MM-Slave per each. From GUI organization it seems that you are assigning MM-Slave to the IRQ, but (as far as I understand it) it works directly opposite: IRQ is tied to MM-Slave and it may has maximum one IRQ. I didn't try to actually run it, but BSP files looks correct and everything compiles at least.
I hope, that there is (or will be) a better way to achieve this.
B. If you can share the same priority between all interrupts, than you can avoid the problem by using only 1 Interrupt Sender and thus only 1 MM-Slave. It works on dev board.
I am working on a boot loader for TMS320DM6437. The idea is to create 2 independent firmware that one will update another. In firmware1 I will download firmware2 file and write it to NOR flash in a specified address. Both firmware are stored in NOR flash in ais format. Now I have two applications in flash. One is my custom boot loader and the second one is my main project. I want to know how I can jump from the first program to the second program located at a specified address. I also expect information about documents which may help me to create custom bootloader
Any recommendations?
You can jump to the entry point. I'm using this approach on TMS320 2802x and 2803x, but it should be the same.
The symbol of the entry point is c_int00.
To get to know the address of c_int00 in the second application, you have to fix the Run-Time Support (RTS) library at a specific address, by modifying the linker command file.
Otherwise you can leave the RTS unconstrained, and create a C variable (at a fixed address) that is initialized with the value of cint_00. Using this method your memory map is more flexible and you can add, togheter with the C variable, a comprehensive data structure with other information for your bootloader, e.g. CRC, version number, etc.
Be carefull with the (re)initialization of the peripherals in the second application, since you are not starting from a hardware reset, and you may need to explicity reset some more registers, or clear interrupt requests.
I am new to the Zedboard and am working up to transferring a complex hardware accelerator I currently have working on a regular FPGA board. Anyway I want to walk before I can run so have done the Zedboard speedway tutorials and am now toying around with small projects. My first of which being an simple adder accelerator:
-Send 2 numbers to the pl(programmable logic), to reg a and b
-the pl adds the numbers
-an interrupt to the PS(CPU) signals the computation has finished.
-In the ISR the PS reads the result from reg c
For this design I am using 3 registers (a,b,c) in the AXI interconnect, I have created the IP templates using CIP.
Basically though what is the best way send a control signal to enable the addition to the PL. So how should I signal to the PL adder that I have loaded the two numbers in reg a and b and now want to add them?
-Should I create a 1bit signal GPIO interconnect, add a 4th 1 bit control register to the IP? or is there a more 'stylish' way to do this by using the BUS2IPdata signals?
-Or is there another way to create custom PS to PL control enable signals?
Many thanks
Sam
Current idea:
-Build a switch in the user_logic HDL based on the BUS2IPWrCE, so when this is asserted to write to reg B I can then signal an enable signal to my adder? Or will I run into some concurrency issues with the data not being fully written straight away?
So to do this I have created the AXI perph using CIP, then modified the used_logic and two new ports, en and interrupt. Following these instructions I employed these external connections.http://www.programmableplanet.com/author.asp?section_id=2142&doc_id=264841
I then connected these two external connections to GPIO interfaces to provide the required functionality.
In your larger designs, it will be difficult to get performance using a GPIOs to control the scheduling of your accelerators. I suggest setting up FIFOs of command blocks between software and hardware.
For example, your peripheral could implement an AXI Stream slave, to receive commands from software, and an AXI Stream master, to send result indications back to software.
It can assert an interrupt to indicate that there are values in the response FIFO.
For higher performance, set up these FIFOs in DRAM and use AXI read/write masters in your peripheral.