Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL.
Investigating a bit further I tried to load just the PLL in modsim and I get the following error.
** Error: (vsim-3039) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/PLL1.vhd(49): Instantiation of 'PLL1_altpll_0' failed.
Region: /pll1
Error loading design
Of the 4 modules seen in the PLL1 entity see below:
Modsim will only except the bottom two. The "pll1_altpll_0" and "pll1_altpll_0_altpll_4242" modules display
Loading PLL1.PLL1_altpll_0_dffpipe_l2c
Loading PLL1.PLL1_altpll_0_altpll_4242
** Error: (vsim-3033) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/submodules/PLL1_altpll_0.v(192): Instantiation of 'cycloneiii_pll' failed. The design unit was not found.
When opened within modsim.
Has anyone had a similar problem or know where I am going wrong using either Modsim or Qsys?
Many Thanks D
Related
I’m new to TinyFPGA, so I need a little help!
I’m working on a Tiny FPGA project for sensors and actuators where each tinyFPGA provides an 8 bit digital sensor input, and a 4 actuators output with different modes of operation (on/off, PWM, and pulses) - they are serially interconnected in a ring using the WS2811 pixel "protocol, and intercepted by a ESP32.
I have successfully built a pretty decent test bench for system simulation which successfully verifies 3 interconnected instances of the design at RTL level (takes 4 hours to complete with my brand new RYZEN 7 machine:-).
Next I want to do is to do post-routing simulation to verify the timing - and here I get stuck. I’m using Lattice Diamond and the “build in” ModelSim.
I want all the testbench logic to be RTL simulated while the actual FPGA design instances to be post-routing/time simulated.
The .mdo script for modelsim generated by Lattice Diamond looks like this:
if {![file exists “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing/timing.mpf”]} {
project new “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing” timing
project addfile “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.vo”
project addfile “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/genericIOSatelite_TB.v”
vlib work
vdel -lib work -all
vlib work
vlog +incdir+C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1 -work work “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.vo”
vlog +incdir+C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2 -work work “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/genericIOSatelite_TB.v”
} else {
project open “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing/timing”
project compileoutofdate
}
vsim -L work -L pmi_work -L ovi_machxo2 +transport_path_delays +transport_int_delays genericIOSatelite_TB -sdfmax /genericIOSatelite_TB/DUT0=C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf
view wave
add wave /*
run 1000ns
Where “genericIOSatelite_impl1_vo.vo” is my routed and placed FPGA design, “genericIOSatelite_TB.v” is my testbench, “genericIOSatelite_impl1_vo.sdf” is the timing database for my FPGA design and “/genericIOSatelite_TB/DUT0” is one out of three testbed instantiations of the FPGA design (eventually I would want all three simulated with timing, but one problem at the time).
Now I get the following errors:
…
Loading instances from C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf
** Error (suppressible): (vsim-SDF-3250) C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf(7071): Failed to find INSTANCE ‘SLICE_303’.
** Error (suppressible): (vsim-SDF-3250) C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf(7082): Failed to find INSTANCE ‘SLICE_304’.
And 100’ds of more errors like this…
But when I look at the first error: “Failed to find INSTANCE ‘SLICE_303’” I don’t understand the issue, I can clearly see the ‘SLICE_303’ instance both in “genericIOSatelite_impl1_vo.sdf” and in “genericIOSatelite_impl1_vo.vo”:
“genericIOSatelite_impl1_vo.sdf”:
.
.
.
(CELL
(CELLTYPE “SLICE_303”)
(INSTANCE SLICE_303)
(DELAY
(ABSOLUTE
(IOPATH B0 F1 (635:710:786)(635:710:786))
(IOPATH A0 F1 (635:710:786)(635:710:786))
(IOPATH FCI F1 (459:514:569)(459:514:569))
)
)
)
.
.
.
“genericIOSatelite_impl1_vo.vo”:
.
.
.
SLICE_303 SLICE_303( .B0(control_7_adj_1162), .A0(cnt_9_adj_1170),
.FCI(n4958), .F1(n312));
.
.
.
I would very much like to get an advise on what I’m doing wrong here, using the inbuilt OSCH with 133 MHZ Freq, and with 7ns cycle time I believe it would be nice with a reassuring post-routing/placement simulation # worst timing.
Best regards/Jonas
It appears to be a bug in ModelSim as suggested in the following article: https://www.intel.com/content/www/us/en/support/programmable/articles/000084538.html
-sdfnoerror -sdfnowarn seems to fix the problem - but not very assuring to just squelch the issues :-(
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance:
SB_HFOSC OSCInst1 (
.CLKHFEN(1'b1),
.CLKHFPU(1'b1),
.CLKHF(CLKLF)
)
I included sb_ice_syn.v file but have a design loading error:
Error: ../testbench/sb_ice_syn.v(26066): Module 'SB_HFOSC_CORE' is not defined
I'm not able to find SB_HFOSC_CORE module in the lattice installation folder.
Where can I find the missed modules?
Doing ModelSim simulation of a Lattice ICE40 family (ICE5LP1K device) design with PLLs requires that a Verilog model of the PLL is included. This is described in Lattice Application Note AN006 (see "c:\lscc\iCEcube2.2015.04\doc\Modelsim_AN006.pdf" for latest iCEcube2 version) on page 9:
If your design contains PLL, add ABIPTBS8.v and ABIWTCZ4.v in $INST_DIR/verilog. For performing Post-Synth simulation for a VHDL design having PLL, you will require a mixed-language simulator, since the PLL model (ABIPTBS8.v) is available only in verilog format.
If the design contains Hardened IP primitives, add the encrypted Verilog simulation library sb_ice_ipenc_modelsim.v available in $INST_DIR/Verilog.
An alternative is if you write a simple simulation model of the SB_HFOSC_CORE PLL core, and then include this in the simulation, since I assume that your focus is on verification of the remaining design, so you probably only need the PLL to give a usable clock.
It is working now.
I found the missing module in the sb_ice_ipenc_modelsim.v
Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.
Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found".
Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" : mm_slave."
I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.
So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?
I have some ideas but don't like them:
Add MM-Slave for each irq (it looks like waste of resources).
Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do?
I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.
Merge all interrupts into one wire (they all will share the same priority).
Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers.
After Component Editor stage is finished Qsys doesn't accept such a system.
Please help.
At last, I have found the following:
A. If you need many IRQ Senders inside one custom Qsys module you need one MM-Slave per each. From GUI organization it seems that you are assigning MM-Slave to the IRQ, but (as far as I understand it) it works directly opposite: IRQ is tied to MM-Slave and it may has maximum one IRQ. I didn't try to actually run it, but BSP files looks correct and everything compiles at least.
I hope, that there is (or will be) a better way to achieve this.
B. If you can share the same priority between all interrupts, than you can avoid the problem by using only 1 Interrupt Sender and thus only 1 MM-Slave. It works on dev board.
When trying to assemble the system according to the instructions in this document
http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf
I get this error message:
Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.nios2_qsys_0.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2_qsys_0.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must declare an associated reset
Warning: System.leds.reset: Interface has no signals
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver
Can you tell me what is wrong?
Since the document uses SOPC Builder, you would need to make certain changes so that it works with QSys without errors.
I have listed the fixes for the errors in your question below:
Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected to instruction_master.
Error: System.nios2_qsys_0: Exception slave sram_0.avalon_slave_0
not connected to instruction_master.
Fix: Connect avalon_slave_0 of the sram to the instruction_master of the nios2_qsys processor.
Error: System.sram.avalon_slave_0: Interface must have an associated clock
Error: System.sram.avalon_slave_0: Interface must have an associated reset
Fix: Edit the de2_sram_controller.vhd file and add the following lines to the signal declarations:
signal clk: in std_logic;
signal reset_n: in std_logic;
Then, edit the sram component you created in QSys and add the clk and reset_n signals.
Error: System.nios2_qsys_0.data_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Error: System.nios2_qsys_0.instruction_master: leds.avalon_slave_0 (0x0..0x3f) overlaps jtag_uart_0.avalon_jtag_slave (0x0..0x7)
Fix: In the QSys window, go to System --> Assign Base Addresses.
Error: System.leds.avalon_slave_0: Interface must have an associated reset
Error: System.sram.avalon_slave_0: sram.avalon_slave_0 must declare an associated reset
Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must
declare an associated reset
Fix: Edit the sram and led components. Under the Interfaces tab make sure Associated Reset has a reset signal (shown in the image below).
Warning: System.leds.reset: Interface has no signals
Fix: Edit the led component. Under the Interfaces tab, towards the bottom, click Remove Interfaces With No Signals.
Warning: System.sram: sram.conduit_end must be exported, or connected to a matching conduit.
Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.
Fix: In the QSys window, for both the sram and led components, under the Export column, ensure you Double-click to export.
Warning: System.jtag_uart_0: Interrupt sender jtag_uart_0.irq is not connected to an interrupt receiver
Fix: Ensure that the avalon_jtag_slave of the jtag_uart_0 is connected to IRQ 31. Refer to the image below and double-click the white circle connecting the jtag_uart_0 to IRQ 31.
I hope this helps.
There is a problem with the sram custom component. It only has a conduit and an Avalon-slave interface, its reset and clock inputs are not visible since the declaration of the component itself is apprently incomplete.
These problems could possibly be fixed by editing the custom component. Right-click the sram component (left pane), Edit -> Interfaces (tab), make sure each interface has a clock and a reset assigned. Once done, generate the component with a new version number, and in Qsys upgrade the component to the edited version (System -> Upgrade IP cores...). Then make sure to connect the clock and reset ports for the sram which should now be visible in Qsys.
There are similar problem with the leds custom component.
It is possible or probable that the above problems are due to trying to use components for SOPC Builder in Qsys
There are also problem with overlapping base adresses. This can be fixed by System -> Assign Base Adresses.
There is an unconnected interrupt as well - scroll right in Qsys so you see the Interrupts column and connect the interrupt between the JTAG UART to the Nios processor.