library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keygeneration is
Port ( key : in STD_LOGIC_VECTOR (127 downto 0);
rc : in STD_LOGIC_VECTOR (3 downto 0);
keyout : out STD_LOGIC_VECTOR (127 downto 0));
end keygeneration;
architecture Behavioral of keygeneration is
component sbox is
port(a: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0));
end component;
component RCON is
Port ( rc : in STD_LOGIC_VECTOR (3 downto 0);
rout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal w0,w1,w2,w3,tem: STD_LOGIC_VECTOR (31 downto 0);
signal rout1: STD_LOGIC_VECTOR (31 downto 0);
begin
-- 52nd line below
w0<=key[127 downto 96];
w1<=key[95 downto 64];
w2<=key[63 downto 32];
w3<=key[31 downto 0];
t1: sbox port map(w3[23 downto 16],tem[31 downto 0]);
t2: sbox port map(w3[15 downto 8],tem[23 downto 16]);
t3: sbox port map(w3[7 downto 0],tem[15 downto 8]);
t4: sbox port map(w3[31 downto 24],tem[7 downto 0]);
r1: RCON port map(rc[3 downto 0],rout1[31 downto 0]);
keyout[127 downto 96]<=w0^tem^rout1;
keyout[95 downto 64]<=w0^tem^rout1^w1;
keyout[63 downto 32]<=w0^tem^rout1^w1^w2;
keyout[31 downto 0]<=w0^tem^rout1^w1^w2^w3;
end Behavioral;
Error found is
ERROR:HDLParsers:164 - "D:/Files/newpro/keygeneration.vhd" Line 52.
parse error, unexpected INTEGER_LITERAL, expecting RETURN or
IDENTIFIER or RSQBRACK.
I have shown the 52nd line in the code. I have got the same error for all the assignment statements from line 52. Please help. Thanks in advance
2 errors:
VHDL does not use [] for indexing arrays (though they are used for signatures). Use () for indexing arrays instead.
There is no ^ operator in VHDL. Use xor instead.
You don't mean this:
w0<=key[127 downto 96];
you mean this:
w0<=key(127 downto 96);
Unlike most counters that i have viewed on this website, my BCD counter requires the use of two 4-Bit adders in order to make 1 8-Bit BCD counter. What I have done so far is design a regular full adder, used that to design a regular 4 bit adder.
This is my code so far:
library ieee;
use ieee.std_logic_1164.all;
entity adder8b_custom is
port(
X: in std_logic_vector( 7 downto 0);
Y: in std_logic_vector (7 downto 0);
S: out std_logic_vector (7 downto 0));
end adder8b_custom;
architecture adder8b_custom of adder8b_custom is
component adder4b
port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_vector (3 downto 0);
C0: in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
C4: out STD_LOGIC);
end component;
signal s1:std_logic_vector ( 7 downto 0); --for addition
signal s2:std_logic_vector ( 7 downto 0); --for subtraction
signal s3, s4, s5, s6: std_logic_vector (3 downto 0);--placeholders
signal i, j, k, l: std_logic;
begin
u1: adder4b port map (X => X (3 downto 0), Y => "0001",c0=>'0', S => s3 (3 downto 0), c4=>i);
s1(3 downto 0) <=s3(3 downto 0) when s3 (3 downto 0) /="1010"
else "0000";
s<=s1;
--u2: adder4b port map (X => X (7 downto 4), Y => "0001" ,c0 => i, S => s4 (3 downto 0), c4=>j);
--s1( 7 downto 4) <= s4( 3 downto 0) when s4( 3 downto 0) /= "1010"
--else "0000";
--s(7 downto 4)<= s1;
end;
As you can see, everything after the signals is messed up and i do know know how to fix it.
I appreciate all input.
If your 4bit adder is working correctly you just need to map carry out from the low nibble to the carry in of the high nibble. Then map your 8bit respectively.
It's been too long since I played with VHDL so I can remember the code you need.
I have a problem with my program in xilinx vhd.
I have to create a processor that supports the classic instructions of MIPS32
add, sub, and, or, lw, sw, sine and cosine. Sine and Cosine will take as argument a number and will return the cos or sin of the angle in ΙΕΕΕ-754 Single precision and Integer from 0 – 1000.
I have an excel file which produce a hex output(for the commands of Mips32) that i use in one components(in InstructionRom)
The input numbers that I want to add or sub or and ..etc..I write them in HEX in the component DataRam.
The problem is with the top component in ReadData1 and ReadData2 I got the same values.
Below I have 2 screenshots and how the top entity is connected with other components.
Other components are working.
Can anyone take a look please?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myTOP is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0);
regA : out STD_LOGIC_VECTOR (31 downto 0);
regB : out STD_LOGIC_VECTOR (31 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
writeReg : out STD_LOGIC_VECTOR (4 downto 0);
Opcode : out STD_LOGIC_VECTOR (5 downto 0);
SinCos : out STD_LOGIC_VECTOR (31 downto 0);
DataOUT : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA2 : out STD_LOGIC_VECTOR (31 downto 0);
WriteData : out STD_LOGIC_VECTOR (31 downto 0));
end myTOP;
architecture Behavioral of myTOP is
component InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myPCRegister is
Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0);
PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
component my_10bitAdder is
Port ( a : in STD_LOGIC_VECTOR (9 downto 0);
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component my_5bitMUX is
Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
b : in STD_LOGIC_VECTOR (4 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component my32to9bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (8 downto 0));
end component;
component my32BitRegistersFile is
Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0);
ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0);
WriteRegister : in STD_LOGIC_VECTOR (4 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
ReadData1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData2 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData3 : out STD_LOGIC_VECTOR (31 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end component;
component myControlUnit is
Port ( A : in STD_LOGIC_VECTOR (5 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
ALUop1 : out STD_LOGIC;
SinCos : out STD_LOGIC;
FI : out STD_LOGIC);
end component;
component my16to32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myALUControl is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : in STD_LOGIC;
op1 : out STD_LOGIC;
op2 : out STD_LOGIC;
bin : out STD_LOGIC);
end component;
component myALU_32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
bin : in STD_LOGIC;
cin : in STD_LOGIC;
op1 : in STD_LOGIC;
op2 : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_SinCos is
Port ( I1 : in STD_LOGIC_VECTOR (8 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
e : out STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_32bitMUX is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal S2, S4, S5, S6, S7, S9 , S10 , S11, S12, S13, S14, S15, S16, S17 : STD_LOGIC_VECTOR(31 downto 0);
signal S0, S1:STD_LOGIC_VECTOR (9 downto 0);
signal S3:STD_LOGIC_VECTOR (4 downto 0);
signal S8:STD_LOGIC_VECTOR (8 downto 0);
signal SC:STD_LOGIC_VECTOR (8 downto 0);
signal SA :STD_LOGIC_VECTOR (2 downto 0);
signal S18:STD_LOGIC;
begin
U0: myPCRegister port map(PC_INPUT=>S1, PC_OUTPUT=>S0, clk=>clk, RESET=>reset);
U1: my_10bitAdder port map (a=>S0, b=>'1', cin=>'0', z=>S1);
U2: InstructionsROM port map(InstructionAddress=>S0 , Instruction=> S2 );
U3: my_5bitMUX port map( a=> S2(15 downto 11), b=>S2(20 downto 16), s=>SC(0), z=>S3);
U4: my32BitRegistersFile port map(ReadRegister1=>S2(25 downto 21), ReadRegister2=>S2(20 downto 16), WriteRegister=>S3, WriteData=>S17, ReadData1=>S5, ReadData2=>S6, RegWrite=>SC(3), clk=>clk, Reset=>reset );
U5: myControlUnit port map(A=>S2(31 downto 26),RegDst=>SC(0), ALUSrc=>SC(1), MemtoReg=>SC(2), RegWrite=>SC(3), MemRead=>SC(4), MemWrite=>SC(5), ALUop1=>SC(6), SinCos=>SC(7), FI=>SC(8));
U6: my16to32bit port map(a=>S2, z=>S4);
U7: myALUControl port map(a=>S2(2 downto 0), s=>SC(6),bin=>SA(0), op1=>SA(1), op2=>SA(2));
U8: my_32bitMUX port map(a=>S4, b=>S6, s=>SC(1), z=>S10);
U9: my_32bitMUX port map(a=>S11, b=>S5, s=>SC(8), z=>S9);
U10: myALU_32bit port map(a=>S9, b=>S10, cin=>'0', bin=>SA(0), op1=>SA(1), op2=>SA(2), z=>S12);
U11: my_32bitMUX port map(a=> S5, b=>S12, s=>SC(8), z=>S7);
U12: my32to9bit port map(a=>S7, z=>S8);
U13: my_SinCos port map(I1=>S8, s=>S2(31 downto 30), e=>S18, O=>S11);
U14: DataRAM port map(DataAddress=>S2(9 downto 0), clk=>clk, readData=>SC(4), writeData=>SC(5), DataIn=>S6, DataOut=>S14);
U15: my_32bitMUX port map(a=>S12, b=>S11, s=>SC(8), z=>S13);
U16: my_32bitMUX port map(a=>S14, b=>S12, s=>SC(2), z=>S15);
U17: my_32bitMUX port map(a=>S11, b=>S15, s=>SC(7), z=>S16);
U18: my_32bitMUX port map(a=>S11, b=>S16, s=>S18, z=>S17);
instruction<=S2;
regA<=S9;
regB<=S10;
ALUout<=S12;
writeReg<=S3;
Opcode<=S2(31 downto 26);
SinCos<= S11;
DataOUT<=S14;
WriteData<=S17;
ReadDATA1<= S5;
ReadDATA2 <=S6;
end Behavioral;
DATARAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end DataRAM;
architecture Behavioral of DataRAM is
-- Define a new type with the name RAM_Array of 8 bits
type RAM_Array is array (0 to 1023)
of std_logic_vector(7 downto 0);
-- Set some initial values in RAM for Testing
signal RAMContent: RAM_Array := (
0 => X"0A", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"05", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"2C", 9 => X"01", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
others => X"00");
begin
-- This process is called when we READ from RAM
p1: process (readData, DataAddress)
begin
if readData = '1' then
DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress));
DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1));
DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2));
DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3));
else
DataOut <= (DataOut'range => 'Z');
end if;
end process;
-- This process is called when we WRITE into RAM
p2: process (clk, writeData)
begin
if (clk'event and clk = '1') then
if writeData ='1' then
RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0);
RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8);
RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16);
RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24);
end if;
end if;
end process;
end Behavioral;
INSTRUCTION ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionsROM;
architecture Behavioral of InstructionsROM is
-- Define a new type with the name ROM_Array of 32 bits
type ROM_Array is array (0 to 1024)
of std_logic_vector(31 downto 0);
-- The data here should be replaced with the intructions in HEX
constant ROMContent: ROM_Array := (
X"8C000000",
X"8C810000",
X"00201822",
X"00201824",
X"00201825",
X"8D000000",
X"8D810000",
X"BC03000A",
X"FC03000A",
X"3C03000A",
X"7C03000A",
others => X"00000000");
begin
Instruction <= ROMContent(conv_integer(InstructionAddress));
end Behavioral;
DataRam and instructionrom were given to us ready ..we just change the values (it depends on what instruction we want to do)
Here are some serious problems with your code:
P1: process sensitivity list should include RAMContent
U1: cout is not connected
U4: readdata3 is not connected
U10: cout is not connected
U14: component my_32bitMUX_937286 is not declared. This gives a compilation error
The first four problems can cause problems without warnings from your simulator. The last is an error and would normally cause your simulator to throw and error and refuse to start the simulation.
How do I split 16-bit data into 2 8-bit data?
signal part : std_logic_vector (16 downto 0);
signal part_1 : std_logic_vector (8 downto 0);
signal part_2 : std_logic_vector (8 downto 0);
The part is actually 17 bit, since 16 downto 0 is a 17 bit range, and the part_* are likewise 9 bit.
If the ranges are 15 downto 0 and 7 downto 0, then you can do the split with:
part_1 <= part( 7 downto 0);
part_2 <= part(15 downto 8);
Btw, quote by Martin Fowler / Phil Karlton:
There are two hard things in computer science:
cache invalidation, naming things, and off-by-one errors.
Why are your signals 17 bits and 9 bits long? I think they should be 16 and 8...
signal part : std_logic_vector (15 downto 0);
signal part_1 : std_logic_vector (7 downto 0);
signal part_2 : std_logic_vector (7 downto 0);
begin -- architecture begin
part_1 <= part(15 downto 8);
part_2 <= part(7 downto 0);
Pretty simple stuff... I'm surprised you didn't run across this in looking at a VHDL example.
There's also aggregate target assignment:
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
type fie is array (natural range 0 to 1) of std_logic_vector (7 downto 0);
signal part: std_logic_vector (15 downto 0);
signal part_1: std_logic_vector (7 downto 0);
signal part_2: std_logic_vector (7 downto 0);
begin
(part_1, part_2) <= fie'(part(15 downto 8), part(7 downto 0));
end architecture;
Which is admittedly more useful for extracting elements of records in one fell swoop. What's slick here is that there's no place there's any named signal of type fie.
The reason for the aggregate on the right hand side is because the element size has to match on both sides of the assignment operator, both aggregates are treated as if they are type fie.
Doing this with records allows you to extract elements of varying sizes. Extracting fields from CPU machine instruction formats comes to mind. It allows you to use simple names without requiring aliases for element selected names. (There would be no named record).
When the element size is the same on both sides you can simply use a target aggregate:
library ieee;
use ieee.std_logic_1164.all;
entity fie is
end entity;
architecture fum of fie is
signal part: std_logic_vector (2 downto 0);
signal part_1: std_logic;
signal part_2: std_logic;
signal part_3: std_logic;
begin
(part_1, part_2, part_3) <= part;
end architecture;
These aggregates all use positional association. You can also use named association. Record aggregates require an others choice represent at least one element and all the elements have to have the same type (e.g. std_logic_vector).
Just for completeness: you can also use aliases which makes the signal assignment obsolete:
signal part : std_logic_vector (15 downto 0);
alias part_1 : std_logic_vector(7 downto 0) is part(15 downto 8);
alias part_2 : std_logic_vector(7 downto 0) is part(7 downto 0);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab3_Adder1 is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Lab3_Adder1;
architecture Behavioral of Lab3_Adder1 is
SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);
begin
c(0) <= cin;
s <= a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
cout <= c(4);
end Behavioral;
Hello, it's the first time im using this forum. I'm doing a wallace tree multiplication on VHDL. The code above is the code for a full adder. I would like to know how do we call a function/component in a main code ? (like in C programing). I would to call this full adder in my main code.
(Sorry for my english if there is any mistake, im french)
You call functions in VHDL just as you do in C - either to initialise constants, signals or variables, or as sequential statements within a process. But that's not important just now.
But you don't call components! That would be like calling an object in C++ - it makes absolutely no sense!
In VHDL you can instantiate components or (simpler!) just entities, and use signals to interconnect their ports. This is (very very crudely) more like declaring objects and sending messages in an object oriented language. This is called "structural VHDL" and often appears at the top level of a VHDL design, to create and interconnect components like CPU, memory interface, FFT processor etc.
Given your entity
entity Lab3_Adder1 is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Lab3_Adder1;
I could build an 8-bit adder for example as follows:
entity Adder_8bit is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
s : out STD_LOGIC_VECTOR (7 downto 0);
cout : out STD_LOGIC);
end Adder_8bit;
architecture Structural of Adder_8bit is
signal carry_int : std_logic; -- between lower and upper halves
begin
-- We need to create and connect up two adders
LSB_adder : entity work.Lab3_Adder1
Port Map(
cin => cin,
a => a(3 downto 0),
b => b(3 downto 0),
s => s(3 downto 0),
cout => carry_int
);
MSB_adder : entity work.Lab3_Adder1
Port Map(
cin => carry_int,
a => a(7 downto 4),
b => b(7 downto 4),
s => s(7 downto 4),
cout => cout
);
end Structural;
You can define VHDL-Functions which replace combinational circuits and which can be called anywhere in the main VHDL-Code similar to C functions.
You need to define a package first where the function definitions go.
======= myAdders.vhdl ==============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
package myAdders is
function Lab3_Adder1( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;
end myAdders;
package body myAdders is
function Lab3_Adder1 ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin
c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;
end myAdders;
======= topLevel.vhdl ==============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.myAddres.all;
entity TopLevel is
Port (
cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0)
);
end TopLevel;
architecture Structural of TopLevel is
signal carry : std_logic;
begin
carry <= Lab3_Adder1(cin, a, b, c);
... and so on ...
end Structural;