vhd xlinix something is wrong same values it must be with muxes - vhdl

Question

I have a problem with my program in xilinx vhd.
I have to create a processor that supports the classic instructions of MIPS32
add, sub, and, or, lw, sw, sine and cosine. Sine and Cosine will take as argument a number and will return the cos or sin of the angle in ΙΕΕΕ-754 Single precision and Integer from 0 – 1000.
I have an excel file which produce a hex output(for the commands of Mips32) that i use in one components(in InstructionRom)
The input numbers that I want to add or sub or and ..etc..I write them in HEX in the component DataRam.
The problem is with the top component in ReadData1 and ReadData2 I got the same values.
Below I have 2 screenshots and how the top entity is connected with other components.
Other components are working.
Can anyone take a look please?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myTOP is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0);
regA : out STD_LOGIC_VECTOR (31 downto 0);
regB : out STD_LOGIC_VECTOR (31 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
writeReg : out STD_LOGIC_VECTOR (4 downto 0);
Opcode : out STD_LOGIC_VECTOR (5 downto 0);
SinCos : out STD_LOGIC_VECTOR (31 downto 0);
DataOUT : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA2 : out STD_LOGIC_VECTOR (31 downto 0);
WriteData : out STD_LOGIC_VECTOR (31 downto 0));
end myTOP;
architecture Behavioral of myTOP is
component InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myPCRegister is
Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0);
PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
component my_10bitAdder is
Port ( a : in STD_LOGIC_VECTOR (9 downto 0);
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component my_5bitMUX is
Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
b : in STD_LOGIC_VECTOR (4 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component my32to9bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (8 downto 0));
end component;
component my32BitRegistersFile is
Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0);
ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0);
WriteRegister : in STD_LOGIC_VECTOR (4 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
ReadData1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData2 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData3 : out STD_LOGIC_VECTOR (31 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end component;
component myControlUnit is
Port ( A : in STD_LOGIC_VECTOR (5 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
ALUop1 : out STD_LOGIC;
SinCos : out STD_LOGIC;
FI : out STD_LOGIC);
end component;
component my16to32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myALUControl is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : in STD_LOGIC;
op1 : out STD_LOGIC;
op2 : out STD_LOGIC;
bin : out STD_LOGIC);
end component;
component myALU_32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
bin : in STD_LOGIC;
cin : in STD_LOGIC;
op1 : in STD_LOGIC;
op2 : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_SinCos is
Port ( I1 : in STD_LOGIC_VECTOR (8 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
e : out STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_32bitMUX is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal S2, S4, S5, S6, S7, S9 , S10 , S11, S12, S13, S14, S15, S16, S17 : STD_LOGIC_VECTOR(31 downto 0);
signal S0, S1:STD_LOGIC_VECTOR (9 downto 0);
signal S3:STD_LOGIC_VECTOR (4 downto 0);
signal S8:STD_LOGIC_VECTOR (8 downto 0);
signal SC:STD_LOGIC_VECTOR (8 downto 0);
signal SA :STD_LOGIC_VECTOR (2 downto 0);
signal S18:STD_LOGIC;
begin
U0: myPCRegister port map(PC_INPUT=>S1, PC_OUTPUT=>S0, clk=>clk, RESET=>reset);
U1: my_10bitAdder port map (a=>S0, b=>'1', cin=>'0', z=>S1);
U2: InstructionsROM port map(InstructionAddress=>S0 , Instruction=> S2 );
U3: my_5bitMUX port map( a=> S2(15 downto 11), b=>S2(20 downto 16), s=>SC(0), z=>S3);
U4: my32BitRegistersFile port map(ReadRegister1=>S2(25 downto 21), ReadRegister2=>S2(20 downto 16), WriteRegister=>S3, WriteData=>S17, ReadData1=>S5, ReadData2=>S6, RegWrite=>SC(3), clk=>clk, Reset=>reset );
U5: myControlUnit port map(A=>S2(31 downto 26),RegDst=>SC(0), ALUSrc=>SC(1), MemtoReg=>SC(2), RegWrite=>SC(3), MemRead=>SC(4), MemWrite=>SC(5), ALUop1=>SC(6), SinCos=>SC(7), FI=>SC(8));
U6: my16to32bit port map(a=>S2, z=>S4);
U7: myALUControl port map(a=>S2(2 downto 0), s=>SC(6),bin=>SA(0), op1=>SA(1), op2=>SA(2));
U8: my_32bitMUX port map(a=>S4, b=>S6, s=>SC(1), z=>S10);
U9: my_32bitMUX port map(a=>S11, b=>S5, s=>SC(8), z=>S9);
U10: myALU_32bit port map(a=>S9, b=>S10, cin=>'0', bin=>SA(0), op1=>SA(1), op2=>SA(2), z=>S12);
U11: my_32bitMUX port map(a=> S5, b=>S12, s=>SC(8), z=>S7);
U12: my32to9bit port map(a=>S7, z=>S8);
U13: my_SinCos port map(I1=>S8, s=>S2(31 downto 30), e=>S18, O=>S11);
U14: DataRAM port map(DataAddress=>S2(9 downto 0), clk=>clk, readData=>SC(4), writeData=>SC(5), DataIn=>S6, DataOut=>S14);
U15: my_32bitMUX port map(a=>S12, b=>S11, s=>SC(8), z=>S13);
U16: my_32bitMUX port map(a=>S14, b=>S12, s=>SC(2), z=>S15);
U17: my_32bitMUX port map(a=>S11, b=>S15, s=>SC(7), z=>S16);
U18: my_32bitMUX port map(a=>S11, b=>S16, s=>S18, z=>S17);
instruction<=S2;
regA<=S9;
regB<=S10;
ALUout<=S12;
writeReg<=S3;
Opcode<=S2(31 downto 26);
SinCos<= S11;
DataOUT<=S14;
WriteData<=S17;
ReadDATA1<= S5;
ReadDATA2 <=S6;
end Behavioral;
DATARAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end DataRAM;
architecture Behavioral of DataRAM is
-- Define a new type with the name RAM_Array of 8 bits
type RAM_Array is array (0 to 1023)
of std_logic_vector(7 downto 0);
-- Set some initial values in RAM for Testing
signal RAMContent: RAM_Array := (
0 => X"0A", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"05", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"2C", 9 => X"01", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
others => X"00");
begin
-- This process is called when we READ from RAM
p1: process (readData, DataAddress)
begin
if readData = '1' then
DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress));
DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1));
DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2));
DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3));
else
DataOut <= (DataOut'range => 'Z');
end if;
end process;
-- This process is called when we WRITE into RAM
p2: process (clk, writeData)
begin
if (clk'event and clk = '1') then
if writeData ='1' then
RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0);
RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8);
RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16);
RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24);
end if;
end if;
end process;
end Behavioral;
INSTRUCTION ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionsROM;
architecture Behavioral of InstructionsROM is
-- Define a new type with the name ROM_Array of 32 bits
type ROM_Array is array (0 to 1024)
of std_logic_vector(31 downto 0);
-- The data here should be replaced with the intructions in HEX
constant ROMContent: ROM_Array := (
X"8C000000",
X"8C810000",
X"00201822",
X"00201824",
X"00201825",
X"8D000000",
X"8D810000",
X"BC03000A",
X"FC03000A",
X"3C03000A",
X"7C03000A",
others => X"00000000");
begin
Instruction <= ROMContent(conv_integer(InstructionAddress));
end Behavioral;
DataRam and instructionrom were given to us ready ..we just change the values (it depends on what instruction we want to do)

Answer 1

Here are some serious problems with your code:
P1: process sensitivity list should include RAMContent
U1: cout is not connected
U4: readdata3 is not connected
U10: cout is not connected
U14: component my_32bitMUX_937286 is not declared. This gives a compilation error
The first four problems can cause problems without warnings from your simulator. The last is an error and would normally cause your simulator to throw and error and refuse to start the simulation.