library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keygeneration is
Port ( key : in STD_LOGIC_VECTOR (127 downto 0);
rc : in STD_LOGIC_VECTOR (3 downto 0);
keyout : out STD_LOGIC_VECTOR (127 downto 0));
end keygeneration;
architecture Behavioral of keygeneration is
component sbox is
port(a: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0));
end component;
component RCON is
Port ( rc : in STD_LOGIC_VECTOR (3 downto 0);
rout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal w0,w1,w2,w3,tem: STD_LOGIC_VECTOR (31 downto 0);
signal rout1: STD_LOGIC_VECTOR (31 downto 0);
begin
-- 52nd line below
w0<=key[127 downto 96];
w1<=key[95 downto 64];
w2<=key[63 downto 32];
w3<=key[31 downto 0];
t1: sbox port map(w3[23 downto 16],tem[31 downto 0]);
t2: sbox port map(w3[15 downto 8],tem[23 downto 16]);
t3: sbox port map(w3[7 downto 0],tem[15 downto 8]);
t4: sbox port map(w3[31 downto 24],tem[7 downto 0]);
r1: RCON port map(rc[3 downto 0],rout1[31 downto 0]);
keyout[127 downto 96]<=w0^tem^rout1;
keyout[95 downto 64]<=w0^tem^rout1^w1;
keyout[63 downto 32]<=w0^tem^rout1^w1^w2;
keyout[31 downto 0]<=w0^tem^rout1^w1^w2^w3;
end Behavioral;
Error found is
ERROR:HDLParsers:164 - "D:/Files/newpro/keygeneration.vhd" Line 52.
parse error, unexpected INTEGER_LITERAL, expecting RETURN or
IDENTIFIER or RSQBRACK.
I have shown the 52nd line in the code. I have got the same error for all the assignment statements from line 52. Please help. Thanks in advance
2 errors:
VHDL does not use [] for indexing arrays (though they are used for signatures). Use () for indexing arrays instead.
There is no ^ operator in VHDL. Use xor instead.
You don't mean this:
w0<=key[127 downto 96];
you mean this:
w0<=key(127 downto 96);
Related
1.8-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M8 is
Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end M8;
architecture Behavioral of M8 is
begin
process(M1,M2)
variable A1: std_logic_vector(17 downto 0);
begin
A1(17 downto 0) := "0000000000" & M1(7 downto 0);
for N in 1 to 9 loop
if A1(0)='1' then
A1(17 downto 9) := A1(17 downto 9) + '0'+ M2(7 downto 0);
end if;
A1(17 downto 0) := '0' & A1(17 downto 1);
end loop;
Mout<= A1(15 downto 0);
end process;
end Behavioral;
2.32-bit multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
Port ( M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0)
);
end M32;
architecture Behavioral of M32 is
begin
process(M1,M2)
variable A1: std_logic_vector(65 downto 0);
begin
A1(65 downto 0) := "0000000000000000000000000000000000" & M1(31 downto 0);
for N in 1 to 33 loop
if A1(0)='1' then
A1(65 downto 33) := A1(65 downto 33) + '0'+ M2(31 downto 0);
end if;
A1(65 downto 0) := '0' & A1(65 downto 1);
end loop;
Mout<= A1(63 downto 0);
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MM32All is
port( MMM1: in std_logic_vector(31 downto 0);
MMM2: in std_logic_vector(31 downto 0);
MMMout: out std_logic_vector(63 downto 0)
);
end MM32All;
architecture Behavioral of MM32All is
component M32 port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end component;
signal MMb: std_logic_vector(31 downto 0);
signal MMa: std_logic_vector(31 downto 0);
signal MMo1: std_logic_vector(39 downto 0);
signal MMo2: std_logic_vector(39 downto 0);
signal MMo3: std_logic_vector(39 downto 0);
signal MMo4: std_logic_vector(39 downto 0);
signal MMout1: std_logic_vector(63 downto 0);
begin
Ma4: M32 port map (MM1=> MMb, MM2=> MMa(31 downto 24), MMout=> MMo4);
Ma3: M32 port map (MM1=> MMb, MM2=> MMa(23 downto 16), MMout=> MMo3);
Ma2: M32 port map (MM1=> MMb, MM2=> MMa(15 downto 8) , MMout=> MMo2);
Ma1: M32 port map (MM1=> MMb, MM2=> MMa(7 downto 0 ) , MMout=> MMo1);
MMout1 <= ("000000000000000000000000" & MMo1) + ("0000000000000000" & MMo2 & "00000000")
+ ("00000000" & MMo3 & "0000000000000000" ) + ( MMo4 & "000000000000000000000000" );
MMb <= MMM1;
MMa <= MMM2;
MMMout <= MMout1;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity M32 is
port(MM1 : in std_logic_vector(31 downto 0);
MM2 : in std_logic_vector(7 downto 0);
MMout:out std_logic_vector(39 downto 0)
);
end M32;
architecture Behavioral of M32 is
component M8 Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8b Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8c Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
component M8d Port ( M1 : in STD_LOGIC_vector(7 downto 0);
M2 : in STD_LOGIC_vector(7 downto 0);
Mout : out STD_LOGIC_vector(15 downto 0)
);
end component;
signal internalMM1: std_logic_vector(31 downto 0);
signal internalMM2: std_logic_vector(7 downto 0);
signal internalMMout: std_logic_vector(39 downto 0);
signal M8dout:std_logic_vector(15 downto 0);
signal M8cout:std_logic_vector(15 downto 0);
signal M8bout:std_logic_vector(15 downto 0);
signal M8out:std_logic_vector(15 downto 0);
begin
--addres: for N in 0 to 3 generate
FulMd32: M8d port map( M1=> internalMM1(31 downto 24), M2=> internalMM2, Mout=> M8dout);
FulMb32: M8b port map( M1=> internalMM1(23 downto 16), M2=> internalMM2, Mout=> M8cout);
FulMc32: M8c port map( M1=> internalMM1(15 downto 8), M2=> internalMM2, Mout=> M8bout);
FulM32: M8 port map( M1=> internalMM1(7 downto 0), M2=> internalMM2, Mout=> M8out);
internalMMout<=("000000000000000000000000" & M8out)
+ ("0000000000000000" & M8bout & "00000000") + ("00000000" & M8cout & "0000000000000000")
+ (M8dout & "000000000000000000000000");
internalMM1 <= MM1;
internalMM2 <= MM2;
MMout <= internalMMout;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
port( A :in std_logic_vector(31 downto 0);
B :in std_logic_vector(31 downto 0);
SS:in std_logic_vector(2 downto 0);
C :out std_logic_vector(63 downto 0);
D :out std_logic_vector(31 downto 0);
La,Sm,Eq: out std_logic);
end ALU;
architecture Behavioral of ALU is
Component M32 is port (M1 : in STD_LOGIC_vector(31 downto 0);
M2 : in STD_LOGIC_vector(31 downto 0);
Mout : out STD_LOGIC_vector(63 downto 0));
end component;
Component SUB32 is port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
OFL:out std_logic;
S : out STD_LOGIC_vector(31 downto 0));
end component;
Component adder32 is Port(A : in STD_LOGIC_vector(31 downto 0);
B : in STD_LOGIC_vector(31 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC_vector(31 downto 0));
end component;
signal aM1,aM2,bM1,bM2,cM1,cM2,cMout,bMout : STD_LOGIC_vector(31 downto 0);
signal aMout: STD_LOGIC_vector(63 downto 0);
signal Overflow: std_logic;
begin
A1: M32 port map( M1=> aM1, M2=>aM2, Mout=>aMout);
A2: SUB32 port map(A=> bM1, B=> bM2, S=>bMout, OFL=>Overflow);
A3: adder32 port map(A=> cM1, B=> cM2, Cout=>open,S=>cMout,Cin=>'0');
process(SS,A,B,Overflow,aMout,bMout,CMout)
begin
Case SS is
When "000"=> aM1<=A;
aM2<=B;
C<=aMout;
When "001" => if Overflow='1' then
bM1<=A;
bM2<=B;
D<=bMout;
else
D<="00000000000000000000000000000000";
end if;
when "010" => cM1<=A;
cM2<=B;
D<= cMout;
when "011" => if (A > B) then
La<='1';
Sm<='0';
Eq<='0';
else if (A<B) then
La<='0';
Sm<='1';
Eq<='0';
else
La<='0';
Sm<='0';
Eq<='1';
end if;
end if;
when "100" =>
D <= (A and B);
when "101" =>
D <= (A or B);
when "110" =>
D <= (A xor B);
When others=> C<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
D<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end case;
end process;
end Behavioral;
32-bit ALU
Based on the Device utilization summary, two designs of multiplier have very similar area utilization. 32-bit multiplier by 8-bit multiplier use about 5% more logic unit than single 32-bit multiplier. The number of used route thru used for 32-bit multiplier by 8-bit multiplier is 238% of single 32-bit multiplier. Even use different design, their performance are the same.
You have very obscure way of doing multiplier as scary_jeff indicates. Most likely the synthesis tool gets confused about that.
Instead of
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Please have
use ieee.numeric_std.all;
and instead of
std_logic_vector(n-1 downto 0)
use
signed(n-1 downto 0);
Then you can just multiply with *.
Off topic, but instead of
D<="00000000000000000000000000000000";
you can use
D <= (others => '0');
I'm trying to simulate a VHDL project but modelsim gives me the following error message:
Error: (vsim-3173) Entity 'C:/Users/chose/Documents/CTD/teste/SELETORES/simulation/modelsim/rtl_work.seletores' has no architecture.
I tryed creatindg another project and it gives me the same error. I was able to sim other projects before, doing the same thing.
I'm running Quartus Prime Lite Edition 16.0 and Modelsim 10.5b. The code i'm trying to simulate is:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity SELETORES is
port( IN_POT: in std_logic;
OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
: in std_logic_vector(9 downto 0);
MODE : in std_logic_vector(39 downto 0);
SEL_DISP, SEL_LED
: in std_logic_vector(1 downto 0);
LED_OUT, SEL_TIME, SEL_POT
: out std_logic_vector(9 downto 0);
REG : out std_logic_vector(19 downto 0)
);
end SELETORES;
architecture SELETORES_bhv of SELETORES is
signal decod_mux : std_logic_vector(19 downto 0);
component mux_4x1_20
port (W,X,Y,Z: in std_logic_vector(19 downto 0);
S: in std_logic_vector(1 downto 0);
F: out std_logic_vector(19 downto 0)
);
end component;
component mux_4x1_10
port (W,X,Y,Z: in std_logic_vector(9 downto 0);
S: in std_logic_vector(1 downto 0);
F: out std_logic_vector(9 downto 0)
);
end component;
component mux_2x1
port (W,X: in std_logic_vector(9 downto 0);
S: in std_logic;
F: out std_logic_vector(9 downto 0)
);
end component;
component decod_time
port( ENTRADA : in std_logic_vector(9 downto 0);
SAIDA: out std_logic_vector(19 downto 0)
);
end component;
begin
L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);
L2 : mux_2x1 port map (SW, MODE(19 downto 10), SEL_DISP(0) and not(SEL_DISP(1)), SEL_TIME);
L3 : decod_time port map (CONTA, decod_mux);
L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);
L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);
end SELETORES_bhv;
First of all you have some syntax errors in your L2 component instantiation. Secondly, in my opinion this is the right way to do it (operators are not permitted in port maps):
library IEEE;
use IEEE.std_logic_1164.all;
entity SELETORES is
port( IN_POT: in std_logic;
OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
: in std_logic_vector(9 downto 0);
MODE : in std_logic_vector(39 downto 0);
SEL_DISP, SEL_LED
: in std_logic_vector(1 downto 0);
LED_OUT, SEL_TIME, SEL_POT
: out std_logic_vector(9 downto 0);
REG : out std_logic_vector(19 downto 0)
);
end SELETORES;
architecture SELETORES_bhv of SELETORES is
-- Component declarations
component mux_4x1_20
port (W,X,Y,Z: in std_logic_vector(19 downto 0);
S1: in std_logic_vector(1 downto 0);
F: out std_logic_vector(19 downto 0)
);
end component;
component mux_4x1_10
port (W,X,Y,Z: in std_logic_vector(9 downto 0);
S2: in std_logic_vector(1 downto 0);
F: out std_logic_vector(9 downto 0)
);
end component;
component mux_2x1
port (W,X: in std_logic_vector(9 downto 0);
S3: in std_logic;
F: out std_logic_vector(9 downto 0)
);
end component;
component decod_time
port(ENTRADA : in std_logic_vector(9 downto 0);
SAIDA: out std_logic_vector(19 downto 0)
);
end component;
--End component declarations
-- Internal signals
signal decod_mux : std_logic_vector(19 downto 0);
signal foobar: std_logic;
--End Internal Signals
begin
foobar <= SEL_DISP(0) AND NOT SEL_DISP(1);
L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);
L2 : mux_2x1 port map (SW, MODE(19 downto 10), foobar, SEL_TIME);
L3 : decod_time port map (CONTA, decod_mux);
L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);
L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);
end SELETORES_bhv;
I've tested on ModelSim 10.1c with no problems.
"Unsigned 8-bit Error Tolerant Adder" to add two 8-bit numbers in "vhdl code". I have already tried the code below.It gives these errors
** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(34): near "Signal": syntax error
** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(41): near "EOF": syntax error
#
code below
enter code here
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity adr is
port (a,b: in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0));
end adr ;
architecture eta of adr is
signal hn,ln: std_logic_vector(7 downto 0);
signal parta2,partb2,hno:std_logic_vector(3 downto 0);
signal parta1,partb1: std_logic_vector(3 downto 0);
signal lno:std_logic_vector(3 downto 0);
begin
process (a,b)
begin
parta1<= a(7 downto 4); -- parta1<= a(7 downto 4);
parta2<= a(3 downto 0); --parta2<= a(3 downto 0);
partb1<= b(7 downto 4); --partb1<= b(7 downto 4);
partb2<= b(3 downto 0); -- partb2<= b(3 downto 0);
hno<= std_logic_vector(unsigned(parta1)+ unsigned(partb1)); --4 bit msb
lno<= std_logic_vector((unsigned(partb2))xor(unsigned(partb2)));--4bit lsb
Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";-- concatenation of hn with zeros
Signal ln: std_logic_vector(7 downto 0) := B"0000" & lno(3 downto 0);--concatenation ln with zeros
output<=(hn or ln);
end process ;
.Thanks in Advance..
OK, you have three issues preventing this from compiling:
Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";
In this line, you have already declared hn, and are trying to declare it again here. You can only declare a signal in the declarative region where most of your signals are defined. The second error is the B"0000"; I suspect you are trying to specify that your literal "0000" is binary, but this is the default when assigning to an std_logic_vector anyway. Your correct line would be:
hn <= hno(3 downto 0) & "0000";
The same errors are present in the line below this one.
The third error is pretty trivial. You have remembered an end process;, but forgotten the end architecture;.
I have a problem with my program in xilinx vhd.
I have to create a processor that supports the classic instructions of MIPS32
add, sub, and, or, lw, sw, sine and cosine. Sine and Cosine will take as argument a number and will return the cos or sin of the angle in ΙΕΕΕ-754 Single precision and Integer from 0 – 1000.
I have an excel file which produce a hex output(for the commands of Mips32) that i use in one components(in InstructionRom)
The input numbers that I want to add or sub or and ..etc..I write them in HEX in the component DataRam.
The problem is with the top component in ReadData1 and ReadData2 I got the same values.
Below I have 2 screenshots and how the top entity is connected with other components.
Other components are working.
Can anyone take a look please?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myTOP is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0);
regA : out STD_LOGIC_VECTOR (31 downto 0);
regB : out STD_LOGIC_VECTOR (31 downto 0);
ALUout : out STD_LOGIC_VECTOR (31 downto 0);
writeReg : out STD_LOGIC_VECTOR (4 downto 0);
Opcode : out STD_LOGIC_VECTOR (5 downto 0);
SinCos : out STD_LOGIC_VECTOR (31 downto 0);
DataOUT : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadDATA2 : out STD_LOGIC_VECTOR (31 downto 0);
WriteData : out STD_LOGIC_VECTOR (31 downto 0));
end myTOP;
architecture Behavioral of myTOP is
component InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myPCRegister is
Port ( PC_INPUT : in STD_LOGIC_VECTOR (9 downto 0);
PC_OUTPUT : out STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
RESET : in STD_LOGIC);
end component;
component my_10bitAdder is
Port ( a : in STD_LOGIC_VECTOR (9 downto 0);
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component my_5bitMUX is
Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
b : in STD_LOGIC_VECTOR (4 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component my32to9bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (8 downto 0));
end component;
component my32BitRegistersFile is
Port ( ReadRegister1 : in STD_LOGIC_VECTOR (4 downto 0);
ReadRegister2 : in STD_LOGIC_VECTOR (4 downto 0);
WriteRegister : in STD_LOGIC_VECTOR (4 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
ReadData1 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData2 : out STD_LOGIC_VECTOR (31 downto 0);
ReadData3 : out STD_LOGIC_VECTOR (31 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC);
end component;
component myControlUnit is
Port ( A : in STD_LOGIC_VECTOR (5 downto 0);
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
ALUop1 : out STD_LOGIC;
SinCos : out STD_LOGIC;
FI : out STD_LOGIC);
end component;
component my16to32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myALUControl is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : in STD_LOGIC;
op1 : out STD_LOGIC;
op2 : out STD_LOGIC;
bin : out STD_LOGIC);
end component;
component myALU_32bit is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
bin : in STD_LOGIC;
cin : in STD_LOGIC;
op1 : in STD_LOGIC;
op2 : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_SinCos is
Port ( I1 : in STD_LOGIC_VECTOR (8 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
e : out STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component my_32bitMUX is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal S2, S4, S5, S6, S7, S9 , S10 , S11, S12, S13, S14, S15, S16, S17 : STD_LOGIC_VECTOR(31 downto 0);
signal S0, S1:STD_LOGIC_VECTOR (9 downto 0);
signal S3:STD_LOGIC_VECTOR (4 downto 0);
signal S8:STD_LOGIC_VECTOR (8 downto 0);
signal SC:STD_LOGIC_VECTOR (8 downto 0);
signal SA :STD_LOGIC_VECTOR (2 downto 0);
signal S18:STD_LOGIC;
begin
U0: myPCRegister port map(PC_INPUT=>S1, PC_OUTPUT=>S0, clk=>clk, RESET=>reset);
U1: my_10bitAdder port map (a=>S0, b=>'1', cin=>'0', z=>S1);
U2: InstructionsROM port map(InstructionAddress=>S0 , Instruction=> S2 );
U3: my_5bitMUX port map( a=> S2(15 downto 11), b=>S2(20 downto 16), s=>SC(0), z=>S3);
U4: my32BitRegistersFile port map(ReadRegister1=>S2(25 downto 21), ReadRegister2=>S2(20 downto 16), WriteRegister=>S3, WriteData=>S17, ReadData1=>S5, ReadData2=>S6, RegWrite=>SC(3), clk=>clk, Reset=>reset );
U5: myControlUnit port map(A=>S2(31 downto 26),RegDst=>SC(0), ALUSrc=>SC(1), MemtoReg=>SC(2), RegWrite=>SC(3), MemRead=>SC(4), MemWrite=>SC(5), ALUop1=>SC(6), SinCos=>SC(7), FI=>SC(8));
U6: my16to32bit port map(a=>S2, z=>S4);
U7: myALUControl port map(a=>S2(2 downto 0), s=>SC(6),bin=>SA(0), op1=>SA(1), op2=>SA(2));
U8: my_32bitMUX port map(a=>S4, b=>S6, s=>SC(1), z=>S10);
U9: my_32bitMUX port map(a=>S11, b=>S5, s=>SC(8), z=>S9);
U10: myALU_32bit port map(a=>S9, b=>S10, cin=>'0', bin=>SA(0), op1=>SA(1), op2=>SA(2), z=>S12);
U11: my_32bitMUX port map(a=> S5, b=>S12, s=>SC(8), z=>S7);
U12: my32to9bit port map(a=>S7, z=>S8);
U13: my_SinCos port map(I1=>S8, s=>S2(31 downto 30), e=>S18, O=>S11);
U14: DataRAM port map(DataAddress=>S2(9 downto 0), clk=>clk, readData=>SC(4), writeData=>SC(5), DataIn=>S6, DataOut=>S14);
U15: my_32bitMUX port map(a=>S12, b=>S11, s=>SC(8), z=>S13);
U16: my_32bitMUX port map(a=>S14, b=>S12, s=>SC(2), z=>S15);
U17: my_32bitMUX port map(a=>S11, b=>S15, s=>SC(7), z=>S16);
U18: my_32bitMUX port map(a=>S11, b=>S16, s=>S18, z=>S17);
instruction<=S2;
regA<=S9;
regB<=S10;
ALUout<=S12;
writeReg<=S3;
Opcode<=S2(31 downto 26);
SinCos<= S11;
DataOUT<=S14;
WriteData<=S17;
ReadDATA1<= S5;
ReadDATA2 <=S6;
end Behavioral;
DATARAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataRAM is
Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
readData : in STD_LOGIC;
writeData : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (31 downto 0);
DataOut : out STD_LOGIC_VECTOR (31 downto 0));
end DataRAM;
architecture Behavioral of DataRAM is
-- Define a new type with the name RAM_Array of 8 bits
type RAM_Array is array (0 to 1023)
of std_logic_vector(7 downto 0);
-- Set some initial values in RAM for Testing
signal RAMContent: RAM_Array := (
0 => X"0A", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"05", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"2C", 9 => X"01", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
others => X"00");
begin
-- This process is called when we READ from RAM
p1: process (readData, DataAddress)
begin
if readData = '1' then
DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress));
DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1));
DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2));
DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3));
else
DataOut <= (DataOut'range => 'Z');
end if;
end process;
-- This process is called when we WRITE into RAM
p2: process (clk, writeData)
begin
if (clk'event and clk = '1') then
if writeData ='1' then
RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0);
RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8);
RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16);
RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24);
end if;
end if;
end process;
end Behavioral;
INSTRUCTION ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsROM is
Port ( InstructionAddress : in STD_LOGIC_VECTOR (9 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionsROM;
architecture Behavioral of InstructionsROM is
-- Define a new type with the name ROM_Array of 32 bits
type ROM_Array is array (0 to 1024)
of std_logic_vector(31 downto 0);
-- The data here should be replaced with the intructions in HEX
constant ROMContent: ROM_Array := (
X"8C000000",
X"8C810000",
X"00201822",
X"00201824",
X"00201825",
X"8D000000",
X"8D810000",
X"BC03000A",
X"FC03000A",
X"3C03000A",
X"7C03000A",
others => X"00000000");
begin
Instruction <= ROMContent(conv_integer(InstructionAddress));
end Behavioral;
DataRam and instructionrom were given to us ready ..we just change the values (it depends on what instruction we want to do)
Here are some serious problems with your code:
P1: process sensitivity list should include RAMContent
U1: cout is not connected
U4: readdata3 is not connected
U10: cout is not connected
U14: component my_32bitMUX_937286 is not declared. This gives a compilation error
The first four problems can cause problems without warnings from your simulator. The last is an error and would normally cause your simulator to throw and error and refuse to start the simulation.
I have this lines of code:
entity test is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
c : out STD_LOGIC_VECTOR (15 downto 0));
end test;
architecture Behavioral of test is
component adder is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
s : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal prod: std_logic_vector (15 downto 0) :=X"0000";
signal tempsum1,tempsum2: std_logic_vector (7 downto 0):=X"00";
signal cin,cout:std_logic:='0';
begin
--Working(modelsim can see the upper value of c)
S1: adder port map(tempsum1, prod(15 downto 8), c(15 downto 8));
--Not working(c gets a red line on all bits):
--I replace the first S1 with this one and assign later.
S1: adder port map(tempsum1, prod(15 downto 8), tempsum2);
c(15 downto 8)<=tempsum2;
end Behavioral;
Can somebody tell me why with the first block of code the c is set and seen in modelsim correctly and with the seccond is not?
Thank you.
Try to suppress the initialization in your signal declaration of tempsum2.