I assume most of you will think I did not try to search on the internet by myself but I really did. I understand nothing on makefile and I tried to create one for c++.
I have only two files: Set.hpp and main.cpp.
Here is my wrong makefile.
CC=g++
CFLAGS= --std=c++0x --pedantic -g -Wall -W
LDFLAGS=
EXEC=main
all: $(EXEC)
main: Set.o main.o
$(CC) -o main Set.o main.o $(LDFLAGS)
main.o: main.cpp
$(CC) -o main.o -c main.cpp $(CFLAGS)
Set.o: Set.hpp
$(CC) -o Set.o -c Set.hpp $(CFLAGS)
clean:
rm -rf *.o
mrproper: clean
rm -rf $(EXEC)
The error I get is simply Make: * no targets. Stop.. I really need help for this please :/ Thank you in advance :)
.hpp files are header files. They are NOT to be complied. They are to be included in the source file. You can find more about the .hpp files and some related info here.
Now, to start with a "working" version of your makefile, let's consider the following points. I assume you have two source files
1. main.cpp
2. Set.cpp
and one header file
1. Set.hpp
in the same directory. Please consider the sample files provided below.
main.cpp
#include <iostream>
#include "Set.hpp"
using namespace std;
int main()
{
call_func();
cout <<"And this is from main.cpp"<<endl<<endl;
return 0;
}
Set.cpp
#include <iostream>
#include "Set.hpp"
using namespace std;
int call_func()
{
cout<<"This is from set.cpp"<<endl<<endl;
return 0;
}
Set.hpp
#include <iostream>
using namespace std;
int call_func();
Makefile
CC=g++
CFLAGS= --std=c++0x --pedantic -g -Wall -W
LDFLAGS=
EXEC=main
all: $(EXEC)
main: Set.o main.o
$(CC) -o main Set.o main.o $(LDFLAGS)
main.o: main.cpp
$(CC) -o main.o -c main.cpp $(CFLAGS)
Set.o: Set.cpp # notice the change from .hpp to .cpp
$(CC) -o Set.o -c Set.cpp $(CFLAGS) # notice the change
clean:
rm -rf *.o
mrproper: clean
rm -rf $(EXEC)
After that, the output is like
[sourav#infba01383 so_overflow]# make
g++ -o Set.o -c Set.cpp --std=c++0x --pedantic -g -Wall -W
g++ -o main.o -c main.cpp --std=c++0x --pedantic -g -Wall -W
g++ -o main Set.o main.o
[sourav#infba01383 so_overflow]# make
make: Nothing to be done for `all'.
[sourav#infba01383 so_overflow]# make clean
rm -rf *.o
[sourav#infba01383 so_overflow]#
Hope this helps!!!
Related
I want to add -std=c++11 to my makefile but I do not Where to add, here is my code:
hw07: test.o functions.o
g++ test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -c functions.cpp
clean:
rm *.o hw07
in the above code where should I add the stdc++11 code, please help me out about...
Instead of spelling out all of the rules and all of the commands, use variables and implicit rules to build your program:
CXXFLAGS = -std=c++11
hw07: test.o functions.o
test.o: test.cpp headerfile.h
functions.o: functions.cpp headerfile.h
clean:
rm *.o hw07
This will have make build the object files using $(CXXFLAGS) as the options to pass to the compiler. Then make will build the program hw07 using the files listed in its dependencies.
Other flags that are good to have when compiling the source files are -Wall and -Wextra. Those enable more warning messages from the compiler, that in almost all cases point out suspect things that could lead to problems.
You can just add -std=c++11 after each g++:
hw07: test.o functions.o
g++ -std=c+++11 test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -std=c+++11 -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -std=c+++11 -c functions.cpp
clean:
rm *.o hw07
Also you can use a variable:
CPP_FLAGS='-std=c++11'
hw07: test.o functions.o
g++ ${CPP_FLAGS} test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ ${CPP_FLAGS} -c test.cpp
functions.o: functions.cpp headerfile.h
g++ ${CPP_FLAGS} -c functions.cpp
clean:
rm *.o hw07
These are my files:
add.c add.h main.c makefile
This is makefile:
main:main.o add.o
gcc -o main main.o add.o
main.o:$(#:%.o=%.c)
gcc -o main.o -c main.c
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
gcc -o add.o -c add.c
.PHONY:clean
clean:
rm *.o -rf
rm main -rf
Then after I change the main.c and make.
But make told me this:
make: `main' is up to date.
If I change my makefile:
main:main.o add.o
gcc -o main main.o add.o
main.o:main.c
gcc -o main.o -c main.c
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
gcc -o add.o -c add.c
.PHONY:clean
clean:
rm *.o -rf
rm main -rf
Then after I change the main.c and make.
It can work.
I donot know the reason.
The dependencies in
main.o:$(#:%.o=%.c)
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
are not valid make syntax.
Replace these two rules with one pattern (generic) rule:
%.o : %.c
gcc -c -o $# ${CPPFLAGS} ${CFLAGS} $<
The above rule is actually very similar to the built-in rule for compiling .o files from .c:
Compiling C programs
n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c.
In other words, you can remove your original rules for main.o and add.o and it should build correctly.
Suppose I have these following c++ files, how should I write a basic makefile for them (using g++)?
a.cpp a.h, b.cpp b.h, c.cpp c.h, main.h
When b.h includes a.h, c.h includes b.h and main.h includes c.h?
thanks a lot
so you can write.
EXE := exe
CC := g++
CPP_FILES := a.cpp b.cpp c.cpp
HPP_FILES := a.h b.h c.h main.h
$(EXE) : $(CPP_FILES) $(HPP_FILES)
$(CC) -o $# $(CPP_FILES)
.PHONY : clean
clean:
rm -rf $(EXE) *.o
How to compile a file? Say you have test.cpp and test.h now, to compile and link it:
g++ -c test.c
g++ -o test test.o
Easiest Makefile:
test: test.o #means test depends on test.o
g++ -o test test.o
test.o: test.cpp test.h #means test.o depends on test.cpp and test.h
g++ -c test.cpp
#if you want clean? add below line too.
clean:
rm test test.o
If your app depends on multiple files, then
test: test1.o test2.o test3.o #means your app depends on test1.o test2.o and test3.o
g++ -o test test1.o test2.o test3.o
test1.o: test1.cpp test1.h
g++ -c test1.cpp
test2.o: test2.cpp test2.h
g++ -c test2.cpp
...
I am trying to add a project's (call it b) code to a different project(call it a). Both projects are compile and run separately. I just copied the folder of project b into project a's folder. In project a's Makefile, I added the lines to compile project b with it. It compiles fine. Now I want to use b's code. But when I try to #include "/bfolder/somefile.h", it cannot find the file. What am I missing about this? If I can just #include "somefileinsamedirectory.h", why can't I do #include "/bfolder/somefile.h"?`
This is a 's Makefile that I have edited to include the irobot_driver code.
INCLUDE = -I/usr/X11R6/include -I/home/sterling/irobot_driver
CC=g++
CFLAGS=-w -D LINUX -fpermissive
CFLAGS_R= -w -D LINUX -O3 -fpermissive
CFLAGS_D=-w -D LINUX -fpermissive
OBJ= obj
OBJ_DEBUG= obj_debug
OBJDIR= release
SRCDIR= src
LDFLAGS= -L/usr/X11R6/lib$(LIBSELECT) -lGL -lfltk -lfltk_gl -lXext -lX11 -lglut -lGLU -lfltk_images
SOURCES_RAW=codeprofiler.cpp gametimer.cpp timer.cpp timeprofile.cpp vector4.cpp matrix.cpp agent.cpp agentcontroller.cpp dummy.cpp evader.cpp pursuer.cpp goal.cpp player.cpp graphdata.cpp graph.cpp cubiccoefs.cpp segment.cpp trajectory.cpp anode.cpp arrayvector4.cpp color.cpp drawcomponent.cpp drawcontroller.cpp flags.cpp global.cpp map_analyzer.cpp minheap.cpp node.cpp quadtree.cpp queue.cpp results.cpp sensor.cpp settings.cpp utility.cpp world.cpp gui.cpp main.cpp logger.cpp parameters.cpp counter.cpp polygon.cpp line.cpp
TARGET:= pursuit_evasion
TARGETD:= pursuit_evasion_d
TARGETP:= pursuit_evasion_p
TARGETW32:= pursuit_evasion_w32
OBJECTS:=$(SOURCES_RAW:.cpp=.o)
OBJECTS:=$(patsubst %.o,$(OBJDIR)/%.o, $(OBJECTS))
SOURCES:=$(SOURCES_RAW)
SOURCES:=$(patsubst %.cpp,$(SRCDIR)/%.cpp, $(SOURCES))
OBJ_DEBUG:=$(SOURCES_RAW:.cpp=.o)
OBJ_DEBUG:=$(patsubst %.o,debug/%.o, $(OBJ_DEBUG))
OBJECTS_P:=$(SOURCES_RAW:.cpp=.o)
OBJECTS_P:=$(patsubst %.o,profile/%.o, $(OBJECTS_P))
OBJDIR=obj
all: $(TARGET)
#--- Release
$(TARGET): $(OBJECTS)
$(CC) -w -D LINUX $(INCLUDE) $^ -o $# $(LDFLAGS)
cd /home/sterling/irobot_driver; sudo make -j2
release/%.o: src/%.cpp
$(CC) -c $< $(CFLAGS_R) -o $#
#--- Debug
debug: $(TARGETD)
$(TARGETD): $(OBJ_DEBUG)
$(CC) -w -D LINUX $(INCLUDE) $^ -o $# $(LDFLAGS)
cd /home/sterling/irobot_driver; sudo make -j2
debug/%.o: src/%.cpp
$(CC) -c -g $< $(CFLAGS)-o $#
#-- Profile
profile: $(TARGETP)
$(TARGETP): $(OBJECTS_P)
$(CC) -w -g -pg -D LINUX $(INCLUDE) $^ -o $# $(LDFLAGS)
profile/%.o: src/%.cpp
$(CC) -c -g -pg $< $(CFLAGS)-o $#
win32: $(TARGETW32)
$(TARGETW32): $(OBJECTS)
$(CC) -w -D WIN32 $(INCLUDE_W32) $^ -o $# $(LDFLAGS)
.PHONY : clean
clean:
rm -f release/*.o
rm -f debug/*.o
rm -f profile/*.o
rm -f $(TARGET) $(TARGETD) $(TARGETP)
cd /home/sterling/irobot_driver; make clean;
The #include "/the/whole/path/to/a/file" that works is -
#include "/home/sterling/irobot_driver/robot_driver_agent.h"
You can, but when you declare the path starting with /some/path/to/file.h it's going to really look for the file at /some/path/to/file.h. If instead you want the bfolder/somefile.h, remove the / from the beginning.
Also, in general, if b is a library that you want to use, it is best to keep it in whatever folder it resides, and include and link using the -I, -L and -l options of gcc, or similar options of other compilers. This way, if you update b you don't need to copy it to every project that uses it.
Try
#include "bfolder/somefile.h"
You are including a leading slash in "/bfolder/somefile.h", which means /bfolder would be in the root directory.
#include "/bfolder/..." would be implying that bfolder is in the root directory of your computer's file system. If bfolder is in the same directory as your source code, then you would just want #include "bfolder/somefile.h"
I am new to using GNU make. I have a makefile as below:
CFLAGS = -c -I $(WXWIN)\include\
hello: main.o
main.o:main.cpp
gcc -c main.cpp
clean:
rm main.o
When I run make command in console it can't find the header file "wx/wx.h". Its location: $(WXWIN)=D:\wxWidgets\
Change your makefile as follows:
CFLAGS = -c -I $(WXWIN)\include
hello: main.o
main.o: main.cpp
gcc $(CFLAGS) main.cpp
clean:
rm main.o