I am new to using GNU make. I have a makefile as below:
CFLAGS = -c -I $(WXWIN)\include\
hello: main.o
main.o:main.cpp
gcc -c main.cpp
clean:
rm main.o
When I run make command in console it can't find the header file "wx/wx.h". Its location: $(WXWIN)=D:\wxWidgets\
Change your makefile as follows:
CFLAGS = -c -I $(WXWIN)\include
hello: main.o
main.o: main.cpp
gcc $(CFLAGS) main.cpp
clean:
rm main.o
Related
I want to add -std=c++11 to my makefile but I do not Where to add, here is my code:
hw07: test.o functions.o
g++ test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -c functions.cpp
clean:
rm *.o hw07
in the above code where should I add the stdc++11 code, please help me out about...
Instead of spelling out all of the rules and all of the commands, use variables and implicit rules to build your program:
CXXFLAGS = -std=c++11
hw07: test.o functions.o
test.o: test.cpp headerfile.h
functions.o: functions.cpp headerfile.h
clean:
rm *.o hw07
This will have make build the object files using $(CXXFLAGS) as the options to pass to the compiler. Then make will build the program hw07 using the files listed in its dependencies.
Other flags that are good to have when compiling the source files are -Wall and -Wextra. Those enable more warning messages from the compiler, that in almost all cases point out suspect things that could lead to problems.
You can just add -std=c++11 after each g++:
hw07: test.o functions.o
g++ -std=c+++11 test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ -std=c+++11 -c test.cpp
functions.o: functions.cpp headerfile.h
g++ -std=c+++11 -c functions.cpp
clean:
rm *.o hw07
Also you can use a variable:
CPP_FLAGS='-std=c++11'
hw07: test.o functions.o
g++ ${CPP_FLAGS} test.o functions.o -o hw07
test.o: test.cpp headerfile.h
g++ ${CPP_FLAGS} -c test.cpp
functions.o: functions.cpp headerfile.h
g++ ${CPP_FLAGS} -c functions.cpp
clean:
rm *.o hw07
I am having issues getting my Makefile to compile a very simple main function, and I can't seem to find the issue. Here is my Makefile:
main: main.o Recursion.o
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
gcc -Wall -c main.c
Recursion.o: Recursion.c Recursion.h
gcc -Wall -c Recursion.c
clean:
rm main *.o
When I enter the make command in the UNIX terminal, this is the result I get:
-bash-4.2$ make
cc -c -o main.o main.c
cc -c -o Recursion.o Recursion.c
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
make: main.o:: Command not found
make: *** [Makefile:3: main] Error 127
-bash-4.2$
I cannot figure out what's wrong. It is generating the executable main, but I'm not sure what exactly the issue is on the command line. Any suggestions?
Makefiles are indentation-sensitive.
Try this:
main: main.o Recursion.o
gcc -Wall -o main main.o Recursion.o
main.o: main.c Recursion.c
gcc -Wall -c main.c
Recursion.o: Recursion.c Recursion.h
gcc -Wall -c Recursion.c
clean:
rm main *.o
I have been fighting with makefile and I need help. I am running a virtual linux window in windows.
from a folder containing my main.c file, I type make and I get
$make
arm-linux-gnueabihf-gcc -g -Wall -I c:\intelFPGA\16.1\embedded\ip\altera\hps\altera_hps\hwlib\include _c main.c -o main.o
process_begin: CreateProcess(NULL, arm-linux-gnueabihf-gcc -g -Wall -I c:\intelFPGA\16.1\embedded\ip\altera\hps\altera_hps\hwlib\include _c main.c -o main.o, ...)failed.
make(e=2): The system cannot find the file specified.
make: *** [main.o] Error 2
This folder contains the following files and an empty folder.
main.c
Makefile
my_first_hps
If I type "where make", I get.
$where make
c:\intelFPGA_lite\16.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin\make.exe
c:\intelFPGA\16.1\quartus\bin64\cygwin\bin\make.exe
c:\Coreutils\bin\make.exe
My Makefile is.
#
TARGET = my_first_hps
#
CROSS_COMPILE = arm-linux-gnueabihf-
CFLAGS = -g -Wall -I ${SOCEDS_DEST_ROOT}c:/intelFPGA/embedded/ip/altera/hps/altera_hps/hwlib/include
LDFLAGS = -g -Wall
CC = $(CROSS_COMPILE)gcc
ARCH= arm
build: $(TARGET)
$(TARGET): main.o
$(CC) $(LDFLAGS) $^ -o $#
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -f $(TARGET) *.a *.o *~
I know it's a bit late but for those who get the same error, I just changed the following line:
CC = $(CROSS_COMPILE)gcc
to
CC = $(CROSS_COMPILE)gcc.exe
which has worked for me. Also don't forget that you should have Altera EDS and DS-5 installed. I installed DS-5 at the same place with EDS:
I'm doing a Makefile to make objects with the same gcc command. This file looks like this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
$(OBJLIB) : $(SRCLIB)
$(CC) $(CCFLAGS) -c $^ -o $#
The objetive is to execute this like:
gcc -Wall -c read_line.c -o read_line.o
gcc -Wall -c client.c -o client.o
But I don't know how to do it, and everything I tested is not working. Is it even possible to do this in a Makefile?
Your makefile expands to this, after the variables are expanded:
main.o srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
In make, using multiple targets in explicit rules like this is the same as writing the rule multiple times, once for each target. So, this is the same as this:
main.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
This means that if either of the source files changes, BOTH object files will be recreated (since each object depends on both sources, not just their own source file).
Further, in your compile line you use the variable $^ which expands to all the prerequisites. So your compile lines will expand to:
gcc -Wall -Werror -c main.c srv.c -o main.o
gcc -Wall -Werror -c main.c srv.c -o srv.o
which is illegal: if you use -c with the -o option you can only compile one source file.
Make has built-in rules that already know how to compile files, so there's no need to write your own. You can just write this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
.PHONY: all
all: $(OBJLIB)
and that's all you need.
These are my files:
add.c add.h main.c makefile
This is makefile:
main:main.o add.o
gcc -o main main.o add.o
main.o:$(#:%.o=%.c)
gcc -o main.o -c main.c
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
gcc -o add.o -c add.c
.PHONY:clean
clean:
rm *.o -rf
rm main -rf
Then after I change the main.c and make.
But make told me this:
make: `main' is up to date.
If I change my makefile:
main:main.o add.o
gcc -o main main.o add.o
main.o:main.c
gcc -o main.o -c main.c
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
gcc -o add.o -c add.c
.PHONY:clean
clean:
rm *.o -rf
rm main -rf
Then after I change the main.c and make.
It can work.
I donot know the reason.
The dependencies in
main.o:$(#:%.o=%.c)
add.o:$(#:%.o=%.c) $(#:%.o=%.h)
are not valid make syntax.
Replace these two rules with one pattern (generic) rule:
%.o : %.c
gcc -c -o $# ${CPPFLAGS} ${CFLAGS} $<
The above rule is actually very similar to the built-in rule for compiling .o files from .c:
Compiling C programs
n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c.
In other words, you can remove your original rules for main.o and add.o and it should build correctly.