My function does not return a value, and I do not understand why? VHDL - vhdl

Question

Part of code in VHDL. Workspace ISE.
My function does not return a value, and I do not understand why
Note that appears to me in ISE is "function 'con_integer14' does not always return a value."
The Function is:
function con_integer14 (vNumberSTD : std_logic_vector(14 downto 0)) return integer is
variable vCounter : integer range 0 to 16 := 0;
variable vNumberINT : integer range 0 to 16384 := 0;
begin
if (vCounter = 0) then
if ((vNumberSTD(vCounter)) = '1') then
vNumberINT := (vNumberINT+(2**vCounter));
elsif ((vNumberSTD(vCounter)) = '0') then
vNumberINT := vNumberINT;
end if;
vCounter := (vCounter+1);
elsif ((vCounter >= 1)or(vCounter < 14)) then
if ((vNumberSTD(vCounter)) = '1') then
vNumberINT := (vNumberINT+(2**vCounter));
elsif ((vNumberSTD(vCounter)) = '0') then
vNumberINT := vNumberINT;
end if;
vCounter := (vCounter+1);
elsif (vCounter = 14) then
if ((vNumberSTD(vCounter)) = '1') then
vNumberINT := (vNumberINT+(2**vCounter));
elsif ((vNumberSTD(vCounter)) = '0') then
vNumberINT := vNumberINT;
end if;
vCounter := (vCounter+1);
elsif (vCounter = 15) then
return vNumberINT;
vCounter := 0;
elsif (vCounter > 15) then
vNumberINT := 0;
vCounter := 0;
end if;
end function con_integer14;
Please help me, thank you :)

Answer 1

I'd go a step further and tell you your function never returns a value. I took the liberty of removing the superfluous parentheses and then took a look at the function's structure.
You're going to execute the first if statement and fail to return a value - there is no return statement in reach.
Add a test bench:
library ieee;
use ieee.std_logic_1164.all;
use work.foo.all;
entity fum is
end entity;
architecture fie of fum is
signal vNumberINT: integer range 0 to 16384;
signal vNumberSTD: std_logic_vector(14 downto 0) := "011001110111100";
begin
CALL:
process
begin
wait for 1 ns;
vNumberINT <= con_integer14(VNumberSTD);
wait for 1 ns;
wait;
end process;
end architecture;
Analyze it, elaborate it and run it:
ghdl -a something.vhdl
david_koontz#Macbook: ghdl -e fum
david_koontz#Macbook: ghdl -r fum
./fum:error: missing return in
function at something.vhdl:10
./fum:error: simulation failed
ghdl: compilation error
And we get it to tell us there's a missing return for the first if statement, that a call to it won't return a value.
To make a conversion routine that converts your std_logic_vector to integer you should use a loop statement with an iteration scheme based on the index range of the input vNumberSTD.
When the loop statement is done 'calculating' vNumberINT return VNumberINT.
Note that if you don't do anything specific about meta values for elements of vNumberSTD they will be treated as '0'.
And with some modifications:
library ieee;
use ieee.std_logic_1164.all;
package foo is
function con_integer14 (vNumberSTD: std_logic_vector(14 downto 0)) return integer;
function conv_slv_int (input: std_logic_vector) return natural;
end package;
package body foo is
function con_integer14 (vNumberSTD : std_logic_vector(14 downto 0)) return integer is
-- variable vCounter: integer range 0 to 16 := 0;
-- variable vNumberINT: integer range 0 to 16384 := 0;
variable vNumberINT: integer range 0 to 32767 := 0;
begin
-- if vCounter = 0 then
-- if vNumberSTD(vCounter) = '1' then
-- vNumberINT := vNumberINT + 2 ** vCounter;
-- elsif vNumberSTD(vCounter) = '0' then
-- vNumberINT := vNumberINT;
-- end if;
-- vCounter := vCounter + 1;
-- elsif vCounter >= 1 or vCounter < 14 then
-- if vNumberSTD(vCounter) = '1' then
-- vNumberINT := vNumberINT + 2 ** vCounter;
-- elsif vNumberSTD(vCounter) = '0' then
-- vNumberINT := vNumberINT;
-- end if;
-- vCounter := vCounter + 1;
-- elsif vCounter = 14 then
-- if vNumberSTD(vCounter) = '1' then
-- vNumberINT := vNumberINT + 2 ** vCounter;
-- elsif vNumberSTD(vCounter) = '0' then
-- vNumberINT := vNumberINT;
-- end if;
-- vCounter := vCounter + 1;
-- elsif vCounter = 15 then
-- return vNumberINT;
-- vCounter := 0;
-- elsif vCounter > 15 then
-- vNumberINT := 0;
-- vCounter := 0;
-- end if;
for i in vNumberSTD'range loop
report "vNumberSTD(" & integer'image(i) & ") = " & std_ulogic'image(vNumberSTD(i));
if vNumberSTD(i) = '1' then
vNumberINT := vNumberINT + 2 ** i;
report "vNumberINT = " & integer'image(vNumberINT);
end if;
end loop;
return vNumberINT;
end function con_integer14;
function conv_slv_int (input: std_logic_vector) return natural is
alias inp: std_logic_vector (input'LENGTH - 1 downto 0) is input;
variable int_equiv: natural range 0 to 2 ** input'LENGTH - 1 := 0;
begin
if Is_X(input) then -- announce meta values - interpreted as '0's
report "conv_slv_int input contains meta value";
end if;
for i in inp'RANGE loop
if To_bit(inp(i)) = '1' then -- convert 'H' to '1', 'L' to '0'
int_equiv := int_equiv + 2 ** i;
end if;
end loop;
return int_equiv;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.foo.all;
entity fum is
end entity;
architecture fie of fum is
signal vNumberINT: integer range 0 to 32767;
signal vNumberSTD: std_logic_vector(14 downto 0) := "HX1001110111100";
begin
CALL:
process
begin
wait for 1 ns;
vNumberINT <= con_integer14(VNumberSTD);
wait for 1 ns;
report "vNumberINT = " &integer'image(vNumberINT);
report "conv_slv_int returns " & integer'image(conv_slv_int(vNumberSTD));
wait;
end process;
end architecture;
Notice I corrected the range of vNumberINT, it can be based on the argument to function con_integer14.
You can remove the report statements in the function. I used them to illustrate the function loop.
I added a second function showing conversion of any length std_logic_vector that will fit in a natural range. It will generate an error when called (function local variables elaborated) if the length of the input won't fit in an integer.
The second function also detects meta value inputs and converts 'H' to '1' and 'L' to '0' for each element of the input.
The use of the alias inp for he input allows us to always deal with the input as natural range, caring about length instead of left and right bounds.
When running the new test bench:
something.vhdl:45:13:#1ns:(report note): vNumberSTD(14) = 'H'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(13) = 'X'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(12) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 4096
something.vhdl:45:13:#1ns:(report note): vNumberSTD(11) = '0'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(10) = '0'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(9) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 4608
something.vhdl:45:13:#1ns:(report note): vNumberSTD(8) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 4864
something.vhdl:45:13:#1ns:(report note): vNumberSTD(7) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 4992
something.vhdl:45:13:#1ns:(report note): vNumberSTD(6) = '0'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(5) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 5024
something.vhdl:45:13:#1ns:(report note): vNumberSTD(4) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 5040
something.vhdl:45:13:#1ns:(report note): vNumberSTD(3) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 5048
something.vhdl:45:13:#1ns:(report note): vNumberSTD(2) = '1'
something.vhdl:48:17:#1ns:(report note): vNumberINT = 5052
something.vhdl:45:13:#1ns:(report note): vNumberSTD(1) = '0'
something.vhdl:45:13:#1ns:(report note): vNumberSTD(0) = '0'
something.vhdl:87:9:#2ns:(report note): vNumberINT = 5052
something.vhdl:59:17:#2ns:(report note): conv_slv_int input contains meta value
something.vhdl:88:9:#2ns:(report note): conv_slv_int returns 21436
We see that you can pass std_logic_vector to both that only conv_slt_int will interpret correctly.

Answer 2

Save yourself some time and use the built-in functions. If you just use numeric_std, then you can do the following:
library IEEE ;
use IEEE.numeric_std.all ;
...
signal Y_int : integer ;
signal A_slv15 : std_logic_vector(14 downto 0) ;
...
Y_int <= to_integer( unsigned( A_slv15) ) ;
If you also include numeric_std_unsigned (warning this is VHDL-2008 and may not yet be supported by your tools - try it and report a bug if it does not work) -
library IEEE ;
use IEEE.numeric_std.all ;
use IEEE.numeric_std_unsigned.all ;
...
signal Y_int : integer ;
signal A_slv15 : std_logic_vector(14 downto 0) ;
...
Y_int <= to_integer( A_slv15) ;

Answer 3

Like what has already been mentioned, you did not cover all possible conditions. It's always good to have a default assignment, either by having an "else" clause, or have a default before the if-elsif statement:
function con_integer14 (...) return integer is
begin
vNumberINT := -1;
if (vCounter = 0) then ...
elsif ...
elsif ... then return vNumberINT;
end if;
return vNumberINT;
end function con_integer14;
or alternatively,
function con_integer14 (...) return integer is
begin
if (vCounter = 0) then ...
elsif ...
elsif ... then return vNumberINT;
else
return vNumberINT;
end if;
end function con_integer14;
I personally prefer the first option, because some tools still complain that not all paths are covered for the second option, though in fact all paths were covered. Anyway, this is just a matter of style.
It seems to me that you are only returning a value when vCounter=15:
elsif (vCounter = 15) then return vNumberINT; ...
and this condition is not always met by your testbench (perhaps never met as analysed by David).
-daniel